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[Infra]: - handle "include" feature for Yosys in running VTR scripts
 - add tests to check the "include" feature works properly for all VTR frontends Signed-off-by: Seyed Alireza Damghani <[email protected]> m
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-43
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9 files changed

+136
-43
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‎.github/workflows/test.yml

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@@ -155,7 +155,7 @@ jobs:
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include: [
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{
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name: 'Basic',
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params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on',
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params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DODIN_USE_YOSYS=ON',
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suite: 'vtr_reg_basic'
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},
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{

‎vtr_flow/benchmarks/hdl_include/include/memory_controller.v

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@@ -24,6 +24,8 @@ reg str_write_enable;
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reg [7:0] str_in;
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wire [7:0] str_out;
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defparam _str.ADDR_WIDTH = 5;
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defparam _str.DATA_WIDTH = 8;
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single_port_ram _str (
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.clk( clk ),
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.addr( str_address ),

‎vtr_flow/scripts/python_libs/vtr/odin/odin.py

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@@ -109,6 +109,9 @@ def run(
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circuit_file :
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Circuit file to optimize
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include_files :
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list of header files
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output_netlist :
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File name to output the resulting circuit to
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‎vtr_flow/scripts/python_libs/vtr/yosys/yosys.py

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@@ -69,7 +69,7 @@ def init_script_file(
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vtr.file_replace(
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yosys_script_full_path,
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{
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"XXX": circuit_list[0],
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"XXX": "{}".format(" ".join(str(s) for s in circuit_list)),
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"YYY": yosys_models_full_path,
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"SSS": yosys_spram_full_path,
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"DDD": yosys_dpram_full_path,
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circuit_file :
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Circuit file to optimize
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include_files :
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list of header files
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output_netlist :
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File name to output the resulting circuit to
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‎vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include/config/config.txt

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This file was deleted.

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_odin/config/config.txt

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#################################################################
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# Configuration file for running experiments #
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# #
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# This config file is testing the ability to specify include #
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# files that should pass to the VTR frontend with the top #
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# module of the benchmark (ch_intrinsic_top.v). This is done #
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# by specifying two Verilog header files that provide essential #
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# definitions, and memory_controller design that provides the #
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# design of an internal component for ch_intrinsic_top. If the #
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# include files are not properly included during compilation #
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# the benchmark is incomplete and the flow will error out. #
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#################################################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/hdl_include
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# Path to directory of includes circuits to use
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includes_dir=benchmarks/hdl_include/include
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# Path to directory of architectures to use
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archs_dir=arch/no_timing/memory_sweep
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# Add circuits to list to sweep
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circuit_list_add=ch_intrinsics_modified.v
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# Add circuits to includes list to sweep
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include_list_add=generic_definitions1.vh
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include_list_add=generic_definitions2.vh
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include_list_add=memory_controller.v
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# Add architectures to list to sweep
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arch_list_add=k4_N10_memSize16384_memData64.xml
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# Parse info and how to parse
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parse_file=vpr_no_timing.txt
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# How to parse QoR info
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qor_parse_file=qor_no_timing.txt
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# Script parameters
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script_params_common=-track_memory_usage --timing_analysis off

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys/config/config.txt

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#################################################################
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# Configuration file for running experiments #
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# #
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# This config file is testing the ability to specify include #
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# files that should pass to the VTR frontend with the top #
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# module of the benchmark (ch_intrinsic_top.v). This is done #
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# by specifying two Verilog header files that provide essential #
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# definitions, and memory_controller design that provides the #
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# design of an internal component for ch_intrinsic_top. If the #
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# include files are not properly included during compilation #
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# the benchmark is incomplete and the flow will error out. #
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#################################################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/hdl_include
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# Path to directory of includes circuits to use
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includes_dir=benchmarks/hdl_include/include
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# Path to directory of architectures to use
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archs_dir=arch/no_timing/memory_sweep
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# Add circuits to list to sweep
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circuit_list_add=ch_intrinsics_modified.v
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# Add circuits to includes list to sweep
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include_list_add=generic_definitions1.vh
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include_list_add=generic_definitions2.vh
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include_list_add=memory_controller.v
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# Add architectures to list to sweep
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arch_list_add=k4_N10_memSize16384_memData64.xml
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# Parse info and how to parse
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parse_file=vpr_no_timing.txt
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# How to parse QoR info
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qor_parse_file=qor_no_timing.txt
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# Script parameters
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script_params_common=-track_memory_usage --timing_analysis off -start yosys

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/hdl_include_yosys_odin/config/config.txt

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#################################################################
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# Configuration file for running experiments #
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# #
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# This config file is testing the ability to specify include #
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# files that should pass to the VTR frontend with the top #
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# module of the benchmark (ch_intrinsic_top.v). This is done #
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# by specifying two Verilog header files that provide essential #
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# definitions, and memory_controller design that provides the #
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# design of an internal component for ch_intrinsic_top. If the #
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# include files are not properly included during compilation #
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# the benchmark is incomplete and the flow will error out. #
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#################################################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/hdl_include
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# Path to directory of includes circuits to use
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includes_dir=benchmarks/hdl_include/include
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# Path to directory of architectures to use
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archs_dir=arch/no_timing/memory_sweep
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# Add circuits to list to sweep
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circuit_list_add=ch_intrinsics_modified.v
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# Add circuits to includes list to sweep
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include_list_add=generic_definitions1.vh
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include_list_add=generic_definitions2.vh
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include_list_add=memory_controller.v
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# Add architectures to list to sweep
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arch_list_add=k4_N10_memSize16384_memData64.xml
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# Parse info and how to parse
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parse_file=vpr_no_timing.txt
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# How to parse QoR info
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qor_parse_file=qor_no_timing.txt
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# Script parameters
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script_params_common=-track_memory_usage --timing_analysis off -elaborator yosys -fflegalize

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/task_list.txt

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regression_tests/vtr_reg_basic/basic_no_timing
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regression_tests/vtr_reg_basic/basic_timing
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regression_tests/vtr_reg_basic/basic_timing_no_sdc
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regression_tests/vtr_reg_basic/hdl_include
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regression_tests/vtr_reg_basic/hdl_include_odin
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regression_tests/vtr_reg_basic/hdl_include_yosys
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regression_tests/vtr_reg_basic/hdl_include_yosys_odin

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