[Infra]: change Yosys standalone synthesis script format to tcl

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

doc/src/yosys/dev_guide.rst

@@ -32,8 +32,8 @@ How to add new changes?
 -----------------------
 
 The Yosys synthesis commands, including the generic synthesis and additional VTR specific configurations, are provided
-in `synthesis.ys <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.ys>`_. To make changes in the overall Yosys synthesis flow, the `synthesis.ys <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.ys>`_
-script is perhaps the first file developers may require to change.
+in `synthesis.tcl <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.tcl>`_. To make changes in the overall Yosys synthesis flow, the `synthesis.tcl <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/synthesis.tcl>`_
+script is perhaps the first file developers may be required to change.
 
 Moreover, the `yosys_models.v <https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/misc/yosyslib/yosys_models.v>`_ file includes the required definitions for Yosys to how it should infer implicit
 memories and instantiate arithmetic operations, such as addition, subtraction, and multiplication. Therefore, to alter these 

doc/src/yosys/structure.rst

@@ -18,7 +18,7 @@ Structure of Yosys Synthesis Files and the Yosys External Library Library
     	│			├── multiply.v
     	│			├── single_port_ram.v
     	│			├── spram_rename.v
-    	│			├── synthesis.ys
+    	│			├── synthesis.tcl
     	│			└── yosys_models.v
     	└── libs
     	    └── EXTERNAL

vtr_flow/misc/yosyslib/synthesis.ys renamed to vtr_flow/misc/yosyslib/synthesis.tcl

@@ -1,18 +1,19 @@
 #################################################################
-# Yosys synthesis script, including generic 'synth' commands, 	#
-# in addition to techmap asynchronous FFs and VTR hard blocks.	#
+# Yosys synthesis script, including generic 'synth' commands,   #
+# in addition to techmap asynchronous FFs and VTR hard blocks.  #
 # Once the VTR flow runs with the Yosys front-end, Yosys        #
-# synthesizes the input design using the following commands. 	#
-#																#
-# NOTE: the script is adapted from the one Eddie Hung proposed 	#
-# for VTR-to-Bitstream[1]. However, a few minor changes to make	#
-# it adaptable with the current VTR flow have been made.		#
-#																#
-# [1] http://eddiehung.github.io/vtb.html						#
-#																#
-# Author: Eddie Hung											#
-# Co-author: Seyed Alireza Damghani	([email protected])  		#
+# synthesizes the input design using the following commands.    #
+#                                                               #
+# NOTE: the script is adapted from the one Eddie Hung proposed  #
+# for VTR-to-Bitstream[1]. However, a few minor changes to make #
+# it adaptable with the current VTR flow have been made.        #
+#                                                               #
+# [1] http://eddiehung.github.io/vtb.html                       #
+#                                                               #
+# Author: Eddie Hung                                            #
+# Co-author: Seyed Alireza Damghani ([email protected])       #
 #################################################################
+yosys -import
 
 # XXX (input circuit) is replaced with filename by the run_vtr_flow script
 read_verilog -sv -nolatches XXX
@@ -23,7 +24,7 @@ read_verilog -sv -nolatches XXX
 # directory for any definitions to modules it doesn't know
 # about, such as hand-instantiated (not inferred) memories
 hierarchy -check -auto-top -libdir .
-proc
+procs
 
 # Check that there are no combinational loops
 scc -select
@@ -50,7 +51,7 @@ techmap -map +/adff2dff.v
 techmap -map TTT/../../../ODIN_II/techlib/adffe2dff.v
 
 # Map multipliers, DSPs, and add/subtracts according to yosys_models.v
-techmap -map YYY */t:$mul */t:$mem */t:$sub */t:$add
+techmap -map YYY */t:\$mul */t:\$mem */t:\$sub */t:\$add
 opt -fast -full
 
 memory_map
@@ -67,15 +68,19 @@ opt -fast
 # as blackboxes
 read_verilog -lib TTT/adder.v
 read_verilog -lib TTT/multiply.v
-read_verilog -lib SSS     #(SSS) will be replaced by single_port_ram.v by python script
-read_verilog -lib DDD     #(DDD) will be replaced by dual_port_ram.v by python script
+#(SSS) will be replaced by single_port_ram.v by python script
+read_verilog -lib SSS
+#(DDD) will be replaced by dual_port_ram.v by python script
+read_verilog -lib DDD
 
 # Rename singlePortRam to single_port_ram
-# Rename dualPortRam to dualZ_port_ram
+# Rename dualPortRam to dual_port_ram
 # rename function of Yosys not work here
 # since it may outcome hierarchy error
-read_verilog SSR         #(SSR) will be replaced by spram_rename.v by python script
-read_verilog DDR         #(DDR) will be replaced by dpram_rename.v by python script
+#(SSR) will be replaced by spram_rename.v by python script
+read_verilog SSR
+#(DDR) will be replaced by dpram_rename.v by python script
+read_verilog DDR
 
 # Flatten the netlist
 flatten

vtr_flow/scripts/python_libs/vtr/paths.py

@@ -19,7 +19,7 @@
 # YOSYS paths
 yosys_exe_path = root_path / "libs" / "EXTERNAL" / "libyosys" / "yosys"
 yosys_lib_path = vtr_flow_path / "misc" / "yosyslib"
-yosys_script_path = yosys_lib_path / "synthesis.ys"
+yosys_script_path = yosys_lib_path / "synthesis.tcl"
 
 # ABC paths
 abc_path = root_path / "abc"

vtr_flow/scripts/python_libs/vtr/yosys/yosys.py

@@ -70,11 +70,11 @@ def init_script_file(
         yosys_script_full_path,
         {
             "XXX": circuit_list[0],
-            "YYY": "./" + YOSYS_LIB_FILES["YSMDL"],
-            "SSS": "./" + YOSYS_LIB_FILES["SPRAM"],
-            "DDD": "./" + YOSYS_LIB_FILES["DPRAM"],
-            "SSR": "./" + YOSYS_LIB_FILES["SPRAMR"],
-            "DDR": "./" + YOSYS_LIB_FILES["DPRAMR"],
+            "YYY": yosys_models_full_path,
+            "SSS": yosys_spram_full_path,
+            "DDD": yosys_dpram_full_path,
+            "SSR": yosys_spram_rename_full_path,
+            "DDR": yosys_dpram_rename_full_path,
             "TTT": str(vtr.paths.yosys_lib_path),
             "ZZZ": output_netlist,
         },
@@ -165,14 +165,14 @@ def run(
         yosys_base_script = str(Path(yosys_script).resolve())
 
     # Copy the script file
-    yosys_script = "synthesis.ys"
+    yosys_script = "synthesis.tcl"
     yosys_script_full_path = str(temp_dir / yosys_script)
     shutil.copyfile(yosys_base_script, yosys_script_full_path)
 
     # Copy the yosys models file
     yosys_models = YOSYS_LIB_FILES["YSMDL"]
     yosys_base_models = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["YSMDL"])
-    yosys_models_full_path = str(temp_dir / yosys_models)
+    yosys_models_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_models)
     shutil.copyfile(yosys_base_models, yosys_models_full_path)
 
     # Copy the VTR memory blocks file
@@ -184,10 +184,10 @@ def run(
     yosys_base_dpram = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["DPRAM"])
     yosys_base_spram_rename = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["SPRAMR"])
     yosys_base_dpram_rename = str(vtr.paths.yosys_lib_path / YOSYS_LIB_FILES["DPRAMR"])
-    yosys_spram_full_path = str(temp_dir / yosys_spram)
-    yosys_dpram_full_path = str(temp_dir / yosys_dpram)
-    yosys_spram_rename_full_path = str(temp_dir / yosys_spram_rename)
-    yosys_dpram_rename_full_path = str(temp_dir / yosys_dpram_rename)
+    yosys_spram_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_spram)
+    yosys_dpram_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_dpram)
+    yosys_spram_rename_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_spram_rename)
+    yosys_dpram_rename_full_path = str(vtr.paths.scripts_path / temp_dir / yosys_dpram_rename)
     shutil.copyfile(yosys_base_spram, yosys_spram_full_path)
     shutil.copyfile(yosys_base_dpram, yosys_dpram_full_path)
     shutil.copyfile(yosys_base_spram_rename, yosys_spram_rename_full_path)
@@ -220,7 +220,7 @@ def run(
         else:
             pass
 
-    cmd += ["-s", yosys_script]
+    cmd += ["-c", yosys_script]
 
     command_runner.run_system_command(
         cmd, temp_dir=temp_dir, log_filename=log_filename, indent_depth=1