Fixed compilation warnings

Nathan Shreve · Nathan Shreve · commit 2f10ec581de7 · 2024-08-20T15:11:27.000-04:00
diff --git a/libs/EXTERNAL/libcatch2 b/libs/EXTERNAL/libcatch2
@@ -1 +1 @@
-Subproject commit 33e24b14fcf95c1c31c8d6b68f445ebb12e026cc
+Subproject commit 4e8d92bf02f7d1c8006a0e7a5ecabd8e62d98502
diff --git a/vpr/src/route/lookahead_profiler.cpp b/vpr/src/route/lookahead_profiler.cpp
@@ -55,14 +55,14 @@ void LookaheadProfiler::record(int iteration,
                                const ParentNetId& net_id,
                                const Netlist<>& net_list,
                                const std::vector<RRNodeId>& branch_inodes) {
-    auto& device_ctx = g_vpr_ctx.device();
-    const auto& rr_graph = device_ctx.rr_graph;
-    auto& route_ctx = g_vpr_ctx.routing();
-
     if (!enabled_)
         return;
 
 #ifdef PROFILE_LOOKAHEAD
+    auto& device_ctx = g_vpr_ctx.device();
+    const auto& rr_graph = device_ctx.rr_graph;
+    auto& route_ctx = g_vpr_ctx.routing();
+
     if (!lookahead_verifier_csv_.is_open()) {
         throw vtr::VtrError("Output file is not open.", "lookahead_profiler.cpp", 67);
     }
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1_odin/arithmetic_tasks/multless_consts/config/golden_results.txt
@@ -1,4 +1,4 @@
-arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_le	num_luts	num_add_blocks	max_add_chain_length	num_sub_blocks	max_sub_chain_length	
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_le	num_luts	num_add_blocks	max_add_chain_length	num_sub_blocks	max_sub_chain_length
 fixed_k6_N8_gate_boost_0.2V_22nm.xml	mult_001.v	common	4.76	vpr	62.50 MiB		0.02	6740	-1	-1	14	0.24	-1	-1	32952	-1	-1	26	32	0	0	success	v8.0.0-10974-gd2d425477-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2024-08-16T10:36:49	betzgrp-wintermute.eecg.utoronto.ca	/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks	64000	32	32	280	312	1	205	90	17	17	289	-1	unnamed_device	24.0 MiB	0.24	1354	8532	2094	5512	926	62.5 MiB	0.09	0.00	8.19013	-165.934	-8.19013	8.19013	0.63	0.000911572	0.000845455	0.0421278	0.0389893	28	3693	28	6.55708e+06	313430	500653.	1732.36	1.79	0.162717	0.142573	21310	115450	-1	3181	20	1654	5188	314521	70762	7.3219	7.3219	-163.86	-7.3219	0	0	612192.	2118.31	0.17	0.11	0.10	-1	-1	0.17	0.037161	0.0324187	186	186	-1	-1	-1	-1	
 fixed_k6_N8_gate_boost_0.2V_22nm.xml	mult_002.v	common	4.52	vpr	62.45 MiB		0.03	6716	-1	-1	14	0.29	-1	-1	32772	-1	-1	30	30	0	0	success	v8.0.0-10974-gd2d425477-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2024-08-16T10:36:49	betzgrp-wintermute.eecg.utoronto.ca	/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks	63948	30	32	277	309	1	215	92	17	17	289	-1	unnamed_device	23.9 MiB	0.40	1292	15824	4267	9033	2524	62.4 MiB	0.15	0.00	8.12966	-162.719	-8.12966	8.12966	0.66	0.000907128	0.000840271	0.0750926	0.0696213	30	3485	28	6.55708e+06	361650	526063.	1820.29	1.22	0.194161	0.171438	21886	126133	-1	2805	18	1296	3712	184432	43269	7.1187	7.1187	-155.263	-7.1187	0	0	666494.	2306.21	0.18	0.08	0.11	-1	-1	0.18	0.0341478	0.0299947	189	189	-1	-1	-1	-1	
 fixed_k6_N8_gate_boost_0.2V_22nm.xml	mult_003.v	common	7.29	vpr	62.25 MiB		0.05	6840	-1	-1	11	0.22	-1	-1	32672	-1	-1	25	32	0	0	success	v8.0.0-10974-gd2d425477-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.4.0 on Linux-4.15.0-213-generic x86_64	2024-08-16T10:36:49	betzgrp-wintermute.eecg.utoronto.ca	/home/singera8/vtr-verilog-to-routing/vtr_flow/tasks	63748	32	32	274	306	1	208	89	17	17	289	-1	unnamed_device	23.8 MiB	0.32	1266	13157	3416	7667	2074	62.3 MiB	0.13	0.00	6.4728	-136.716	-6.4728	6.4728	0.63	0.000893199	0.000827038	0.0631231	0.0583866	36	3746	35	6.55708e+06	301375	612192.	2118.31	4.11	0.262229	0.228441	22750	144809	-1	3090	21	1352	4535	306541	80605	6.05052	6.05052	-138.923	-6.05052	0	0	782063.	2706.10	0.21	0.11	0.13	-1	-1	0.21	0.0390401	0.0341413	180	180	-1	-1	-1	-1	

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		-arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length
	`1`	+arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length
`2`	`2`	fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 4.76 vpr 62.50 MiB 0.02 6740 -1 -1 14 0.24 -1 -1 32952 -1 -1 26 32 0 0 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64000 32 32 280 312 1 205 90 17 17 289 -1 unnamed_device 24.0 MiB 0.24 1354 8532 2094 5512 926 62.5 MiB 0.09 0.00 8.19013 -165.934 -8.19013 8.19013 0.63 0.000911572 0.000845455 0.0421278 0.0389893 28 3693 28 6.55708e+06 313430 500653. 1732.36 1.79 0.162717 0.142573 21310 115450 -1 3181 20 1654 5188 314521 70762 7.3219 7.3219 -163.86 -7.3219 0 0 612192. 2118.31 0.17 0.11 0.10 -1 -1 0.17 0.037161 0.0324187 186 186 -1 -1 -1 -1
`3`	`3`	fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 4.52 vpr 62.45 MiB 0.03 6716 -1 -1 14 0.29 -1 -1 32772 -1 -1 30 30 0 0 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63948 30 32 277 309 1 215 92 17 17 289 -1 unnamed_device 23.9 MiB 0.40 1292 15824 4267 9033 2524 62.4 MiB 0.15 0.00 8.12966 -162.719 -8.12966 8.12966 0.66 0.000907128 0.000840271 0.0750926 0.0696213 30 3485 28 6.55708e+06 361650 526063. 1820.29 1.22 0.194161 0.171438 21886 126133 -1 2805 18 1296 3712 184432 43269 7.1187 7.1187 -155.263 -7.1187 0 0 666494. 2306.21 0.18 0.08 0.11 -1 -1 0.18 0.0341478 0.0299947 189 189 -1 -1 -1 -1
`4`	`4`	fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 7.29 vpr 62.25 MiB 0.05 6840 -1 -1 11 0.22 -1 -1 32672 -1 -1 25 32 0 0 success v8.0.0-10974-gd2d425477-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-08-16T10:36:49 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 63748 32 32 274 306 1 208 89 17 17 289 -1 unnamed_device 23.8 MiB 0.32 1266 13157 3416 7667 2074 62.3 MiB 0.13 0.00 6.4728 -136.716 -6.4728 6.4728 0.63 0.000893199 0.000827038 0.0631231 0.0583866 36 3746 35 6.55708e+06 301375 612192. 2118.31 4.11 0.262229 0.228441 22750 144809 -1 3090 21 1352 4535 306541 80605 6.05052 6.05052 -138.923 -6.05052 0 0 782063. 2706.10 0.21 0.11 0.13 -1 -1 0.21 0.0390401 0.0341413 180 180 -1 -1 -1 -1