Merge branch 'master' into feature_router_lookahead_verifier

Author: Nathan Shreve

doc/src/arch/index.rst

@@ -4,7 +4,7 @@ FPGA Architecture Description
 =============================
 
 VTR uses an XML-based architecture description language to describe the targeted FPGA architecture.
-This flexible description langauge allows the user to describe a large number of hypothetical and commercial-like FPGA architectures.
+This flexible description language allows the user to describe a large number of hypothetical and commercial-like FPGA architectures.
 
 See the :ref:`arch_tutorial` for an introduction to the architecture description langauge.
 For a detailed reference on the supported options see the :ref:`arch_reference`.

doc/src/arch/reference.rst

@@ -2036,6 +2036,12 @@ The ``<segment>`` tag and its contents are described below.
 
     Tag must be included and ``name`` must be the same as the name you give in ``<switch type="mux" name="...``
 
+.. arch:tag:: <mux_inter_die name="string"/>
+
+    :req_param name: Name of the mux switch type used to drive this segment type when the driver (block outputs and other wires) is located on a different die than the segment. This information is utilized during rr-graph construction.
+
+    Tag must be included and ``name`` must be the same as the name you give in ``<switch type="mux" name="...``
+
 .. arch:tag:: <wire_switch name="string"/>
 
     :req_param name: Name of the switch type used by other wires to drive this type of segment by default. This information is used during rr-graph construction, and a custom switch block can override this switch type for specific connections if desired.

doc/src/quickstart/index.rst

@@ -2,22 +2,22 @@
 VTR Quick Start
 ###############
 
-This is a quick introduction to VTR which covers how to run VTR and some if its associated tools (:ref:`VPR`, :ref:`odin_ii`, :ref:`ABC`).
+This is a quick introduction to VTR which covers how to run VTR and some of its associated tools (:ref:`VPR`, :ref:`odin_ii`, :ref:`ABC`).
 
 Setting Up VTR
 ==============
 
 Download VTR
 ------------
 
-The first step is to `download VTR <https://verilogtorouting.org/download/>`_ and extract VTR on your local machine.
+The first step is to `download VTR <https://verilogtorouting.org/download/>`_ and extract it on your local machine.
 
 .. note:: Developers planning to modify VTR should clone the `VTR git repository <https://github.com/verilog-to-routing/vtr-verilog-to-routing/>`_.
 
 
 Environment Setup
 -----------------
-If you cloned the repository you will need to set up the git submodules (if you downloaded and extracted a release, you can skip this step):
+If you cloned the repository, you will need to set up the git submodules (if you downloaded and extracted a release, you can skip this step):
 
 .. code-block:: bash
 
@@ -77,12 +77,12 @@ For more details on building VTR on various operating systems/platforms see :doc
 Running VPR
 ===========
 
-Lets now try taking a simple pre-synthesized circuit (consisting of LUTs and Flip-Flops) and use the VPR tool to implement it on a specific FPGA architecture.
+Let's now try taking a simple pre-synthesized circuit (consisting of LUTs and Flip-Flops) and use the VPR tool to implement it on a specific FPGA architecture.
 
 Running VPR on a Pre-Synthesized Circuit
 ----------------------------------------
 
-First, lets make a directory in our home directory where we can work:
+First, let's make a directory in our home directory where we can work:
 
 .. code-block:: bash
 
@@ -211,13 +211,13 @@ Running the VTR Flow
 In the previous section we have implemented a pre-synthesized circuit onto a pre-existing FPGA architecture using VPR, and visualized the result.
 We now turn to how we can implement *our own circuit* on a pre-existing FPGA architecture.
 
-To do this we begin by describing a circuit behaviourly using the Verilog Hardware Description Language (HDL).
+To do this, we begin by describing a circuit behaviourally using the Verilog Hardware Description Language (HDL).
 This allows us to quickly and consisely define the circuit's behaviour.
 We will then use the VTR Flow to synthesize the behavioural Verilog description it into a circuit netlist, and implement it onto an FPGA.
 
 Example Circuit
 ---------------
-We will use the following simple example circuit, which causes it's output to toggle on and off:
+We will use the following simple example circuit, which causes its output to toggle on and off:
 
 .. literalinclude:: blink.v
     :language: verilog
@@ -230,7 +230,7 @@ If the count is below ``16`` it drives the output (``o_led``) high, otherwise it
 
 Manually Running the VTR Flow
 -----------------------------
-Lets start by making a fresh directory for us to work in:
+Let's start by making a fresh directory for us to work in:
 
 .. code-block:: bash
 
@@ -241,15 +241,15 @@ Next we need to run the three main sets of tools:
 
 * :ref:`odin_ii` performs 'synthesis' which converts our behavioural Verilog (``.v`` file) into a circuit netlist (``.blif`` file) consisting of logic equations and FPGA architecture primitives (Flip-Flops, adders etc.),
 * :ref:`ABC` performs 'logic optimization' which simplifies the circuit logic, and 'technology mapping' which converts logic equations into the Look-Up-Tables (LUTs) available on an FPGA, and
-* :ref:`VPR` which performs packing, placement and routing of the circuit to implement it on the targetted FPGA architecture.
+* :ref:`VPR` which performs packing, placement and routing of the circuit to implement it on the targeted FPGA architecture.
 
 .. _synthesizing_with_odin_ii:
 Synthesizing with ODIN II
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 
 First we'll run ODIN II on our Verilog file to synthesize it into a circuit netlist, providing the options:
 
- * ``-a $VTR_ROOT/vtr_flow/arch/timing/EArch.xml`` which specifies what FPGA architecture we are targetting,
+ * ``-a $VTR_ROOT/vtr_flow/arch/timing/EArch.xml`` which specifies what FPGA architecture we are targeting,
  * ``-V $VTR_ROOT/doc/src/quickstart/blink.v`` which specifies the verilog file we want to synthesize, and
  * ``-o blink.odin.blif`` which specifies the name of the generated ``.blif`` circuit netlist.
 
@@ -400,7 +400,7 @@ Automatically Running the VTR Flow
 Running each stage of the flow manually is time consuming (and potentially error prone).
 For convenience, VTR provides a script (:ref:`run_vtr_flow`) which automates this process.
 
-First, make sure you sure you have activated the Python virtual environment created at the beginning of this tutorial:
+First, make sure you have activated the Python virtual environment created at the beginning of this tutorial:
 
 .. code-block:: bash
 

doc/src/vpr/file_formats.rst

@@ -623,7 +623,11 @@ All the following lines have the format::
 
     block_name    x        y   subtile_number
 
-The ``block_name`` is the name of this block, as given in the input .net formatted netlist.
+The ``block_name`` can refer to either:
+
+- The name of a clustered block, as given in the input .net formatted netlist.
+- The name of a primitive within a clustered block.
+
 ``x`` and ``y`` are the row and column in which the block is placed, respectively.
 
 .. note:: The blocks in a placement file can be listed in any order.

doc/src/vpr/vpr_constraints.rst

@@ -2,9 +2,7 @@ VPR Constraints
 =========================
 .. _vpr_constraints:
 
-VPR allows users to run the flow with placement constraints that enable primitives to be locked down to a specific region on the chip and global routing constraints that facilitate the routing of global nets through clock networks.
-
-Users can specify these constraints through a constraints file in XML format, as shown in the format below.
+Users can specify placement and/or global routing constraints on all or part of a design through a constraints file in XML format, as shown in the format below. These constraints are optional and allow detailed control of the region on the chip in which parts of the design are placed, and of the routing of global nets through dedicated (usually clock) networks. 
 
 .. code-block:: xml
    :caption: The overall format of a VPR constraints file

libs/EXTERNAL/libcatch2

@@ -606,7 +606,7 @@ Time TimingReporter::report_timing_data_arrival_subpath(std::ostream& os,
 
     {
         //Input constraint
-        TATUM_ASSERT(subpath.elements().size() > 0);
+        TATUM_ASSERT(!subpath.elements().empty());
         const TimingPathElem& path_elem = *(subpath.elements().begin());
 
         Time input_constraint;
@@ -712,7 +712,7 @@ bool TimingReporter::nearly_equal(const Time& lhs, const Time& rhs) const {
 
 size_t TimingReporter::estimate_point_print_width(const TimingPath& path) const {
     size_t width = 60; //default
-    for(auto subpath : {path.clock_launch_path(), path.data_arrival_path(), path.clock_capture_path()}) {
+    for(const auto& subpath : {path.clock_launch_path(), path.data_arrival_path(), path.clock_capture_path()}) {
         for(auto elem : subpath.elements()) {
             //Take the longest typical point name
             std::string point = name_resolver_.node_name(elem.node()) + " (" + name_resolver_.node_type_name(elem.node()) + ")";

libs/EXTERNAL/libtatum/libtatum/tatum/TimingReporter.cpp

@@ -15,8 +15,9 @@
 #include "vtr_memory.h"
 #include "vtr_strong_id_range.h"
 #include "vtr_array_view.h"
-#include<iostream>
+#include <iostream>
 #include <optional>
+#include <cstdint>
 
 /* Main structure describing one routing resource node.  Everything in       *
  * this structure should describe the graph -- information needed only       *

libs/librrgraph/src/base/rr_graph_storage.h

@@ -7,6 +7,7 @@
 #include <vector>
 #include <array>
 #include <map>
+#include <cstdint>
 #include "vtr_range.h"
 #include "vtr_ndmatrix.h"
 

libs/librrgraph/src/base/rr_node_types.h

@@ -2,4 +2,4 @@
 `rr_graph_uxsdcxx_interface.h` are generated via uxsdcxx and are checked in to
 avoid requiring python3 and the uxsdcxx depedencies to build VPR.
 
-See `vpr/src/route/gen/SCHEMA_GENERATOR.md` for details.
+See `$VTR_DIR/libs/librrgraph/src/base/SCHEMA_GENERATOR.md` for details.

libs/librrgraph/src/io/gen/README.gen.md

@@ -4,9 +4,9 @@
  * https://github.com/duck2/uxsdcxx
  * Modify only if your build process doesn't involve regenerating this file.
  *
- * Cmdline: /home/talaeikh/uxsdcxx/uxsdcxx.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
+ * Cmdline: uxsdcxx/uxsdcxx.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
  */
 
 #include <functional>
@@ -247,8 +247,8 @@ constexpr const char *atok_lookup_t_segment_timing[] = {"C_per_meter", "R_per_me
 
 enum class gtok_t_segment {TIMING};
 constexpr const char *gtok_lookup_t_segment[] = {"timing"};
-enum class atok_t_segment {ID, NAME, RES_TYPE};
-constexpr const char *atok_lookup_t_segment[] = {"id", "name", "res_type"};
+enum class atok_t_segment {ID, LENGTH, NAME, RES_TYPE};
+constexpr const char *atok_lookup_t_segment[] = {"id", "length", "name", "res_type"};
 
 enum class gtok_t_segments {SEGMENT};
 constexpr const char *gtok_lookup_t_segments[] = {"segment"};
@@ -792,6 +792,24 @@ inline atok_t_segment lex_attr_t_segment(const char *in, const std::function<voi
 		default: break;
 		}
 		break;
+	case 6:
+		switch(*((triehash_uu32*)&in[0])){
+		case onechar('l', 0, 32) | onechar('e', 8, 32) | onechar('n', 16, 32) | onechar('g', 24, 32):
+			switch(in[4]){
+			case onechar('t', 0, 8):
+				switch(in[5]){
+				case onechar('h', 0, 8):
+					return atok_t_segment::LENGTH;
+				break;
+				default: break;
+				}
+			break;
+			default: break;
+			}
+		break;
+		default: break;
+		}
+		break;
 	case 8:
 		switch(*((triehash_uu64*)&in[0])){
 		case onechar('r', 0, 64) | onechar('e', 8, 64) | onechar('s', 16, 64) | onechar('_', 24, 64) | onechar('t', 32, 64) | onechar('y', 40, 64) | onechar('p', 48, 64) | onechar('e', 56, 64):
@@ -2325,7 +2343,7 @@ inline void load_switch_required_attributes(const pugi::xml_node &root, int * id
 }
 
 inline void load_segment_required_attributes(const pugi::xml_node &root, int * id, const std::function<void(const char *)> * report_error){
-	std::bitset<3> astate = 0;
+	std::bitset<4> astate = 0;
 	for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){
 		atok_t_segment in = lex_attr_t_segment(attr.name(), report_error);
 		if(astate[(int)in] == 0) astate[(int)in] = 1;
@@ -2334,6 +2352,9 @@ inline void load_segment_required_attributes(const pugi::xml_node &root, int * i
 		case atok_t_segment::ID:
 			*id = load_int(attr.value(), report_error);
 			break;
+		case atok_t_segment::LENGTH:
+			/* Attribute length set after element init */
+			break;
 		case atok_t_segment::NAME:
 			/* Attribute name set after element init */
 			break;
@@ -2343,7 +2364,7 @@ inline void load_segment_required_attributes(const pugi::xml_node &root, int * i
 		default: break; /* Not possible. */
 		}
 	}
-	std::bitset<3> test_astate = astate | std::bitset<3>(0b100);
+	std::bitset<4> test_astate = astate | std::bitset<4>(0b1010);
 	if(!test_astate.all()) attr_error(test_astate, atok_lookup_t_segment, report_error);
 }
 
@@ -2936,6 +2957,9 @@ inline void load_segment(const pugi::xml_node &root, T &out, Context &context, c
 		case atok_t_segment::ID:
 			/* Attribute id is already set */
 			break;
+		case atok_t_segment::LENGTH:
+			out.set_segment_length(load_int(attr.value(), report_error), context);
+			break;
 		case atok_t_segment::NAME:
 			out.set_segment_name(attr.value(), context);
 			break;
@@ -4006,6 +4030,8 @@ inline void write_segments(T &in, std::ostream &os, Context &context){
 			auto child_context = in.get_segments_segment(i, context);
 			os << "<segment";
 			os << " id=\"" << in.get_segment_id(child_context) << "\"";
+			if((bool)in.get_segment_length(child_context))
+				os << " length=\"" << in.get_segment_length(child_context) << "\"";
 			os << " name=\"" << in.get_segment_name(child_context) << "\"";
 			if((bool)in.get_segment_res_type(child_context))
 				os << " res_type=\"" << lookup_segment_res_type[(int)in.get_segment_res_type(child_context)] << "\"";

libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h

@@ -4,9 +4,9 @@
  * https://github.com/duck2/uxsdcxx
  * Modify only if your build process doesn't involve regenerating this file.
  *
- * Cmdline: /home/talaeikh/uxsdcxx/uxsdcap.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
+ * Cmdline: uxsdcxx/uxsdcap.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
  */
 
 #include <functional>
@@ -601,6 +601,7 @@ inline void load_segment_capnp_type(const ucap::Segment::Reader &root, T &out, C
 	(void)report_error;
 	(void)stack;
 
+	out.set_segment_length(root.getLength(), context);
 	out.set_segment_name(root.getName().cStr(), context);
 	out.set_segment_res_type(conv_enum_segment_res_type(root.getResType(), report_error), context);
 	stack->push_back(std::make_pair("getTiming", 0));
@@ -1101,6 +1102,8 @@ inline void write_segments_capnp_type(T &in, ucap::Segments::Builder &root, Cont
 		auto segments_segment = segments_segments[i];
 		auto child_context = in.get_segments_segment(i, context);
 		segments_segment.setId(in.get_segment_id(child_context));
+		if((bool)in.get_segment_length(child_context))
+			segments_segment.setLength(in.get_segment_length(child_context));
 		segments_segment.setName(in.get_segment_name(child_context));
 		if((bool)in.get_segment_res_type(child_context))
 			segments_segment.setResType(conv_to_enum_segment_res_type(in.get_segment_res_type(child_context)));

libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h

@@ -4,9 +4,9 @@
  * https://github.com/duck2/uxsdcxx
  * Modify only if your build process doesn't involve regenerating this file.
  *
- * Cmdline: /home/talaeikh/uxsdcxx/uxsdcxx.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
+ * Cmdline: uxsdcxx/uxsdcxx.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
  */
 
 #include <functional>
@@ -245,11 +245,14 @@ class RrGraphBase {
 	 *     <xs:element minOccurs="0" name="timing" type="segment_timing" />
 	 *   </xs:all>
 	 *   <xs:attribute name="id" type="xs:int" use="required" />
+	 *   <xs:attribute name="length" type="xs:int" />
 	 *   <xs:attribute name="name" type="xs:string" use="required" />
 	 *   <xs:attribute name="res_type" type="segment_res_type" />
 	 * </xs:complexType>
 	*/
 	virtual inline int get_segment_id(typename ContextTypes::SegmentReadContext &ctx) = 0;
+	virtual inline int get_segment_length(typename ContextTypes::SegmentReadContext &ctx) = 0;
+	virtual inline void set_segment_length(int length, typename ContextTypes::SegmentWriteContext &ctx) = 0;
 	virtual inline const char * get_segment_name(typename ContextTypes::SegmentReadContext &ctx) = 0;
 	virtual inline void set_segment_name(const char * name, typename ContextTypes::SegmentWriteContext &ctx) = 0;
 	virtual inline enum_segment_res_type get_segment_res_type(typename ContextTypes::SegmentReadContext &ctx) = 0;

libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h

@@ -155,6 +155,7 @@
       <xs:element name="timing" type="segment_timing" minOccurs="0"/>
     </xs:all>
     <xs:attribute name="id" type="xs:int" use="required"/>
+    <xs:attribute name="length" type="xs:int"/>
     <xs:attribute name="name" type="xs:string" use="required"/>
     <xs:attribute name="res_type" type="segment_res_type"/>
   </xs:complexType>

libs/librrgraph/src/io/rr_graph.xsd

@@ -1347,13 +1347,23 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
     inline const char* get_segment_name(const t_segment_inf*& segment) final {
         return segment->name.c_str();
     }
+    inline int get_segment_length(const t_segment_inf*& segment) final {
+        return segment->length;
+    }
     inline void set_segment_name(const char* name, const t_segment_inf*& segment) final {
         if (segment->name != name) {
             report_error(
                 "Architecture file does not match RR graph's segment name: arch uses %s, RR graph uses %s",
                 segment->name.c_str(), name);
         }
     }
+    inline void set_segment_length(int length, const t_segment_inf*& segment) final {
+        if (segment->length != length) {
+            report_error(
+                "Architecture file does not match RR graph's length: arch uses %d, RR graph uses %d",
+                segment->length, length);
+        }
+    }
     inline uxsd::enum_segment_res_type get_segment_res_type(const t_segment_inf*& segment) final {
         return to_uxsd_segment_res_type(segment->res_type);
     }