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Copy file name to clipboardExpand all lines: doc/src/odin/dev_guide/contributing.md
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@@ -28,14 +28,18 @@ Make changes to that branch.
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Then, create a pull request with that branch and **include WIP in the title.**
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This will automatically indicate that this PR is not ready to be merged.
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Continue to work on the branch, pushing the commits regularly.
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Like a PR, test cases are also needed to be included through the use of benchmarks.
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Like a PR, test cases must be included through the use of benchmarks.
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See [regression tests](./regression_tests) for further instruction.
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### Formating
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Odin II shares the same contributing philosophy as [VPR](https://docs.verilogtorouting.org/en/latest/dev/contributing/contributing/).
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Most importantly PRs will be rejected if they do not respect the coding standard: see [VPRs coding standard](https://docs.verilogtorouting.org/en/latest/dev/developing/#code-formatting)
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To correct any code formatting issues flagged by the CI system, simply run ``make format`` to adapt the newly added code to VPR's coding standard.
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If you have made alterations to python scripts, you would probably need to run ``make format-py`` and ``./dev/pylint_check.py`` from the VTR root directory to correct the python code formatting and check for lint errors.
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## Odin II's Flow
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Odin II functions by systematically executing a set of steps determined by the files and arguments passed in.
The verify_odin.sh script will simulate the microbenchmarks and a larger set of benchmark circuits.
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The ``verify_odin.sh`` script will simulate the microbenchmarks and a larger set of benchmark circuits.
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These scripts use simulation results which have been verified against ModelSim.
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After you build Odin II, run 'make test' to ensure that everything is working correctly on your system.
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Unlike the verify\_regression\_tests.sh script, verify\_odin.sh also simulates the
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blif output, as well as simulating the verilog with and without the
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After you build Odin-II, run ``make test ELABORATOR=odin`` or ``make test`` to ensure that everything is working correctly on your system.
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The ``verify_odin.sh`` also simulates the blif output, as well as simulating the verilog with and without the
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architecture file.
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Before checking in any changes to Odin II, please run both of these scripts to ensure that both of these scripts execute correctly.
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If there is a failure, use ModelSim to verify that the failure is within Odin II and not a faulty regression test.
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If it is a faulty regression test, make an [issue on GitHub](./reporting_bugs.md).
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The Odin II simulator will produce a test.do file containing clock and input vector information for ModelSim.
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If it is a faulty regression test, make an [issue on GitHub](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new/choose).
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The Odin II simulator will produce a ``test.do`` file containing clock and input vector information for ModelSim.
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When additional circuits are found to agree with ModelSim, they should be added to the regression tests.
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When new features are added to Odin II, new microbenchmarks should be developed which test those features for regression.
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Load the Verilog circuit into a new project in ModelSim.
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Compile the circuit, and load the resulting library for simulation.
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You may use random vectors via the -g option, or specify your own input vectors using the -t option.
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When simulation is complete, load the resulting test.do file into your ModelSim project and execute it.
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You may now directly compare the vectors in the output\_vectors file with those produced by ModelSim.
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You may use random vectors via the ``-g`` option, or specify your own input vectors using the ``-t`` option.
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When simulation is complete, load the resulting ``test.do`` file into your ModelSim project and execute it.
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You may now directly compare the vectors in the ``output_vectors`` file with those produced by ModelSim.
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> NOTE
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>
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> For simulation purposes, you may need to handle the ``GLOBAL_SIM_BASE_CLK`` signal in the ``input_vector`` by either adding this signal as an input signal to the top module or removing it from the ``input_vector`` file.
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To add the verified vectors and circuit to an existing test set, move the verilog file (eg: test\_circuit.v) to the test set folder.
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Next, move the input\_vectors file to the test set folder, and rename it test\_circuit\_input. Finally, move the output\_vectors file to the test set folder and rename it test\_circuit\_output.
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To add the verified vectors and circuit to an existing test set, move the Verilog file (eg: ``test_circuit.v``) to the test set folder.
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Next, move the ``input_vectors`` file to the test set folder, and rename it ``test_circuit_$ELABORATOR_input`` (`$ELABORATOR: odin, yosys`). Finally, move the ``output_vectors`` file to the test set folder and rename it ``test_circuit_$ELABORATOR_output``.
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