Merge pull request #1908 from ethanroj23/rr_graph_node_ptc_num

RRGraphView node_ptc_num(), node_pin_num(), node_class_num(), node_track_num() Implementation

Author: tangxifan

utils/fasm/test/test_fasm.cpp

@@ -193,7 +193,7 @@ static std::string get_pin_feature (size_t inode) {
     int ilow = rr_graph.node_xlow(RRNodeId(inode));
     int jlow = rr_graph.node_ylow(RRNodeId(inode));
     auto physical_tile = device_ctx.grid[ilow][jlow].type;
-    int pin_num = device_ctx.rr_nodes[inode].ptc_num();
+    int pin_num = rr_graph.node_pin_num(RRNodeId(inode));
 
     // Get the sub tile (type, not instance) and index of its pin that matches
     // the node index.

vpr/src/base/read_route.cpp

@@ -249,7 +249,6 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
         } else if (tokens[0] == "Node:") {
             /*An actual line, go through each node and add it to the route tree*/
             inode = atoi(tokens[1].c_str());
-            auto node = device_ctx.rr_nodes[inode];
 
             /*First node needs to be source. It is isolated to correctly set heap head.*/
             if (node_count == 0 && tokens[2] != "SOURCE") {
@@ -309,7 +308,7 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
             }
 
             ptc = atoi(tokens[5 + offset].c_str());
-            if (node.ptc_num() != ptc) {
+            if (rr_graph.node_ptc_num(RRNodeId(inode)) != ptc) {
                 vpr_throw(VPR_ERROR_ROUTE, filename, lineno,
                           "The ptc num of node %d does not match the rr graph", inode);
             }
@@ -318,7 +317,7 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
             if (tokens[6 + offset] != "Switch:") {
                 /*This is an opin or ipin, process its pin nums*/
                 if (!is_io_type(device_ctx.grid[x][y].type) && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) {
-                    int pin_num = device_ctx.rr_nodes[inode].ptc_num();
+                    int pin_num = rr_graph.node_pin_num(RRNodeId(inode));
 
                     auto type = device_ctx.grid[x][y].type;
                     int height_offset = device_ctx.grid[x][y].height_offset;

vpr/src/device/rr_graph_view.h

@@ -249,6 +249,38 @@ class RRGraphView {
         return node_storage_.node_side_string(node);
     }
 
+    /** @brief The ptc_num carries different meanings for different node types 
+     * (true in VPR RRG that is currently supported, may not be true in customized RRG) 
+     * CHANX or CHANY: the track id in routing channels 
+     * OPIN or IPIN: the index of pins in the logic block data structure 
+     * SOURCE and SINK: the class id of a pin (indicating logic equivalence of pins) in the logic block data structure  
+     * @note  
+     * This API is very powerful and developers should not use it unless it is necessary, 
+     * e.g the node type is unknown. If the node type is known, the more specific routines, `node_pin_num()`, 
+     * `node_track_num()`and `node_class_num()`, for different types of nodes should be used.*/
+
+    inline short node_ptc_num(RRNodeId node) const {
+        return node_storage_.node_ptc_num(node);
+    }
+
+    /** @brief Get the pin num of a routing resource node. This is designed for logic blocks, 
+     * which are IPIN and OPIN nodes. This function is inlined for runtime optimization. */
+    inline short node_pin_num(RRNodeId node) const {
+        return node_storage_.node_pin_num(node);
+    }
+
+    /** @brief Get the track num of a routing resource node. This is designed for routing tracks, 
+     * which are CHANX and CHANY nodes. This function is inlined for runtime optimization. */
+    inline short node_track_num(RRNodeId node) const {
+        return node_storage_.node_track_num(node);
+    }
+
+    /** @brief Get the class num of a routing resource node. This is designed for routing source and sinks,
+     *  which are SOURCE and SINK nodes. This function is inlined for runtime optimization. */
+    inline short node_class_num(RRNodeId node) const {
+        return node_storage_.node_class_num(node);
+    }
+
     /** @brief Get the cost index of a routing resource node. This function is inlined for runtime optimization. */
     RRIndexedDataId node_cost_index(RRNodeId node) const {
         return node_storage_.node_cost_index(node);

vpr/src/draw/draw.cpp

@@ -1686,12 +1686,12 @@ static void draw_rr_edges(int inode, ezgl::renderer* g) {
         return; /* Nothing to draw. */
     }
 
-    from_ptc_num = device_ctx.rr_nodes[inode].ptc_num();
+    from_ptc_num = rr_graph.node_ptc_num(RRNodeId(inode));
 
     for (t_edge_size iedge = 0, l = device_ctx.rr_nodes[inode].num_edges(); iedge < l; iedge++) {
         to_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
         to_type = rr_graph.node_type(RRNodeId(to_node));
-        to_ptc_num = device_ctx.rr_nodes[to_node].ptc_num();
+        to_ptc_num = rr_graph.node_ptc_num(RRNodeId(to_node));
         bool edge_configurable = device_ctx.rr_nodes[inode].edge_is_configurable(iedge);
 
         switch (from_type) {
@@ -2193,18 +2193,18 @@ ezgl::rectangle draw_get_rr_chan_bbox(int inode) {
                     + draw_coords->get_tile_width();
             bottom = draw_coords->tile_y[rr_graph.node_ylow(rr_node)]
                      + draw_coords->get_tile_width()
-                     + (1. + device_ctx.rr_nodes[inode].ptc_num());
+                     + (1. + rr_graph.node_track_num(rr_node));
             top = draw_coords->tile_y[rr_graph.node_ylow(rr_node)]
                   + draw_coords->get_tile_width()
-                  + (1. + device_ctx.rr_nodes[inode].ptc_num());
+                  + (1. + rr_graph.node_track_num(rr_node));
             break;
         case CHANY:
             left = draw_coords->tile_x[rr_graph.node_xlow(rr_node)]
                    + draw_coords->get_tile_width()
-                   + (1. + device_ctx.rr_nodes[inode].ptc_num());
+                   + (1. + rr_graph.node_track_num(rr_node));
             right = draw_coords->tile_x[rr_graph.node_xlow(rr_node)]
                     + draw_coords->get_tile_width()
-                    + (1. + device_ctx.rr_nodes[inode].ptc_num());
+                    + (1. + rr_graph.node_track_num(rr_node));
             bottom = draw_coords->tile_y[rr_graph.node_ylow(rr_node)];
             top = draw_coords->tile_y[rr_graph.node_yhigh(rr_node)]
                   + draw_coords->get_tile_width();
@@ -2257,7 +2257,7 @@ static void draw_rr_pin(int inode, const ezgl::color& color, ezgl::renderer* g)
     auto& device_ctx = g_vpr_ctx.device();
     const auto& rr_graph = device_ctx.rr_graph;
 
-    int ipin = device_ctx.rr_nodes[inode].ptc_num();
+    int ipin = rr_graph.node_pin_num(RRNodeId(inode));
 
     g->set_color(color);
 
@@ -2305,7 +2305,7 @@ void draw_get_rr_pin_coords(const t_rr_node& node, float* xcen, float* ycen, con
     xc = draw_coords->tile_x[i];
     yc = draw_coords->tile_y[j];
 
-    ipin = node.ptc_num();
+    ipin = rr_graph.node_pin_num(rr_node);
     type = device_ctx.grid[i][j].type;
     pins_per_sub_tile = type->num_pins / type->capacity;
     k = ipin / pins_per_sub_tile;
@@ -2352,6 +2352,7 @@ static void draw_rr_src_sink(int inode, ezgl::color color, ezgl::renderer* g) {
     t_draw_coords* draw_coords = get_draw_coords_vars();
 
     auto& device_ctx = g_vpr_ctx.device();
+    const auto& rr_graph = device_ctx.rr_graph;
 
     float xcen, ycen;
     draw_get_rr_src_sink_coords(device_ctx.rr_nodes[inode], &xcen, &ycen);
@@ -2363,7 +2364,7 @@ static void draw_rr_src_sink(int inode, ezgl::color color, ezgl::renderer* g) {
         {xcen + draw_coords->pin_size, ycen + draw_coords->pin_size});
 
     std::string str = vtr::string_fmt("%d",
-                                      device_ctx.rr_nodes[inode].ptc_num());
+                                      rr_graph.node_class_num(RRNodeId(inode)));
     g->set_color(ezgl::BLACK);
     g->draw_text({xcen, ycen}, str.c_str(), 2 * draw_coords->pin_size,
                  2 * draw_coords->pin_size);
@@ -2389,8 +2390,8 @@ static void draw_get_rr_src_sink_coords(const t_rr_node& node, float* xcen, floa
         class_per_height = num_class / (height - 1);
     }
 
-    int class_height_offset = node.class_num() / class_per_height; //Offset wrt block height
-    int class_height_shift = node.class_num() % class_per_height;  //Offset within unit block
+    int class_height_offset = rr_graph.node_class_num(rr_node) / class_per_height; //Offset wrt block height
+    int class_height_shift = rr_graph.node_class_num(rr_node) % class_per_height;  //Offset within unit block
 
     float xc = draw_coords->tile_x[rr_graph.node_xlow(rr_node)];
     float yc = draw_coords->tile_y[rr_graph.node_ylow(rr_node) + class_height_offset];
@@ -2619,7 +2620,7 @@ static int get_track_num(int inode, const vtr::OffsetMatrix<int>& chanx_track, c
     RRNodeId rr_node = RRNodeId(inode);
 
     if (get_draw_state_vars()->draw_route_type == DETAILED)
-        return (device_ctx.rr_nodes[inode].ptc_num());
+        return (rr_graph.node_track_num(rr_node));
 
     /* GLOBAL route stuff below. */
 
@@ -2765,7 +2766,7 @@ static int draw_check_rr_node_hit(float click_x, float click_y) {
                 t_physical_tile_type_ptr type = device_ctx.grid[i][j].type;
                 int width_offset = device_ctx.grid[i][j].width_offset;
                 int height_offset = device_ctx.grid[i][j].height_offset;
-                int ipin = device_ctx.rr_nodes[inode].ptc_num();
+                int ipin = rr_graph.node_pin_num(rr_node);
                 float xcen, ycen;
                 for (const e_side& iside : SIDES) {
                     // If pin exists on this side of the block, then get pin coordinates
@@ -3141,10 +3142,11 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
     auto& device_ctx = g_vpr_ctx.device();
     const auto& rr_graph = device_ctx.rr_graph;
 
-    const t_rr_node& pin_rr = device_ctx.rr_nodes[pin_node];
-    const t_rr_node& chan_rr = device_ctx.rr_nodes[chan_node];
+    //const t_rr_node& pin_rr = device_ctx.rr_nodes[pin_node];
+    auto pin_rr = RRNodeId(pin_node);
+    auto chan_rr = RRNodeId(chan_node);
 
-    const t_grid_tile& grid_tile = device_ctx.grid[rr_graph.node_xlow(pin_rr.id())][rr_graph.node_ylow(pin_rr.id())];
+    const t_grid_tile& grid_tile = device_ctx.grid[rr_graph.node_xlow(pin_rr)][rr_graph.node_ylow(pin_rr)];
     t_physical_tile_type_ptr grid_type = grid_tile.type;
 
     float x1 = 0, y1 = 0;
@@ -3186,8 +3188,8 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
      */
     std::vector<e_side> pin_candidate_sides;
     for (const e_side& pin_candidate_side : SIDES) {
-        if ((rr_graph.is_node_on_specific_side(pin_rr.id(), pin_candidate_side))
-            && (grid_type->pinloc[grid_tile.width_offset][grid_tile.height_offset][pin_candidate_side][pin_rr.pin_num()])) {
+        if ((rr_graph.is_node_on_specific_side(pin_rr, pin_candidate_side))
+            && (grid_type->pinloc[grid_tile.width_offset][grid_tile.height_offset][pin_candidate_side][rr_graph.node_pin_num(pin_rr)])) {
             pin_candidate_sides.push_back(pin_candidate_side);
         }
     }
@@ -3200,13 +3202,13 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
         pin_side = pin_candidate_sides[0];
     } else {
         VTR_ASSERT(1 < pin_candidate_sides.size());
-        if (CHANX == channel_type && rr_graph.node_ylow(pin_rr.id()) <= rr_graph.node_ylow(chan_rr.id())) {
+        if (CHANX == channel_type && rr_graph.node_ylow(pin_rr) <= rr_graph.node_ylow(chan_rr)) {
             pin_side = TOP;
-        } else if (CHANX == channel_type && rr_graph.node_ylow(pin_rr.id()) - 1 >= rr_graph.node_ylow(chan_rr.id())) {
+        } else if (CHANX == channel_type && rr_graph.node_ylow(pin_rr) - 1 >= rr_graph.node_ylow(chan_rr)) {
             pin_side = BOTTOM;
-        } else if (CHANY == channel_type && rr_graph.node_xlow(pin_rr.id()) <= rr_graph.node_xlow(chan_rr.id())) {
+        } else if (CHANY == channel_type && rr_graph.node_xlow(pin_rr) <= rr_graph.node_xlow(chan_rr)) {
             pin_side = RIGHT;
-        } else if (CHANY == channel_type && rr_graph.node_xlow(pin_rr.id()) - 1 >= rr_graph.node_xlow(chan_rr.id())) {
+        } else if (CHANY == channel_type && rr_graph.node_xlow(pin_rr) - 1 >= rr_graph.node_xlow(chan_rr)) {
             pin_side = LEFT;
         }
         /* The inferred side must be in the list of sides of the pin rr_node!!! */
@@ -3259,7 +3261,7 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
             y1 += draw_pin_offset;
             y2 = chan_bbox.bottom();
             x2 = x1;
-            if (is_opin(pin_rr.pin_num(), grid_type)) {
+            if (is_opin(rr_graph.node_pin_num(pin_rr), grid_type)) {
                 if (chan_rr_direction == Direction::INC) {
                     x2 = chan_bbox.left();
                 } else if (chan_rr_direction == Direction::DEC) {
@@ -3272,7 +3274,7 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
             x1 += draw_pin_offset;
             x2 = chan_bbox.left();
             y2 = y1;
-            if (is_opin(pin_rr.pin_num(), grid_type)) {
+            if (is_opin(rr_graph.node_pin_num(pin_rr), grid_type)) {
                 if (chan_rr_direction == Direction::INC) {
                     y2 = chan_bbox.bottom();
                 } else if (chan_rr_direction == Direction::DEC) {
@@ -3289,7 +3291,7 @@ static void draw_pin_to_chan_edge(int pin_node, int chan_node, ezgl::renderer* g
     g->draw_line({x1, y1}, {x2, y2});
 
     //don't draw the ex, or triangle unless zoomed in really far
-    if (chan_rr_direction == Direction::BIDIR || !is_opin(pin_rr.pin_num(), grid_type)) {
+    if (chan_rr_direction == Direction::BIDIR || !is_opin(rr_graph.node_pin_num(pin_rr), grid_type)) {
         draw_x(x2, y2, 0.7 * draw_coords->pin_size, g);
     } else {
         float xend = x2 + (x1 - x2) / 10.;

vpr/src/draw/search_bar.cpp

@@ -192,7 +192,7 @@ void auto_zoom_rr_node(int rr_node_id) {
             t_physical_tile_type_ptr type = device_ctx.grid[i][j].type;
             int width_offset = device_ctx.grid[i][j].width_offset;
             int height_offset = device_ctx.grid[i][j].height_offset;
-            int ipin = device_ctx.rr_nodes[rr_node_id].ptc_num();
+            int ipin = rr_graph.node_ptc_num(RRNodeId(rr_node_id));
             float xcen, ycen;
 
             for (const e_side& iside : SIDES) {

vpr/src/route/check_route.cpp

@@ -214,7 +214,7 @@ static void check_source(RRNodeId inode, ClusterNetId net_id) {
     int i = rr_graph.node_xlow(inode);
     int j = rr_graph.node_ylow(inode);
     /* for sinks and sources, ptc_num is class */
-    int ptc_num = device_ctx.rr_nodes[size_t(inode)].ptc_num();
+    int ptc_num = rr_graph.node_class_num(inode);
     /* First node_block for net is the source */
     ClusterBlockId blk_id = cluster_ctx.clb_nlist.net_driver_block(net_id);
     auto type = device_ctx.grid[i][j].type;
@@ -325,18 +325,20 @@ static bool check_adjacent(int from_node, int to_node) {
 
     num_adj = 0;
 
-    from_type = rr_graph.node_type(RRNodeId(from_node));
-    from_xlow = rr_graph.node_xlow(RRNodeId(from_node));
-    from_ylow = rr_graph.node_ylow(RRNodeId(from_node));
-    from_xhigh = rr_graph.node_xhigh(RRNodeId(from_node));
-    from_yhigh = rr_graph.node_yhigh(RRNodeId(from_node));
-    from_ptc = device_ctx.rr_nodes[from_node].ptc_num();
-    to_type = rr_graph.node_type(RRNodeId(to_node));
-    to_xlow = rr_graph.node_xlow(RRNodeId(to_node));
-    to_ylow = rr_graph.node_ylow(RRNodeId(to_node));
-    to_xhigh = rr_graph.node_xhigh(RRNodeId(to_node));
-    to_yhigh = rr_graph.node_yhigh(RRNodeId(to_node));
-    to_ptc = device_ctx.rr_nodes[to_node].ptc_num();
+    auto from_rr = RRNodeId(from_node);
+    auto to_rr = RRNodeId(to_node);
+    from_type = rr_graph.node_type(from_rr);
+    from_xlow = rr_graph.node_xlow(from_rr);
+    from_ylow = rr_graph.node_ylow(from_rr);
+    from_xhigh = rr_graph.node_xhigh(from_rr);
+    from_yhigh = rr_graph.node_yhigh(from_rr);
+    from_ptc = rr_graph.node_ptc_num(from_rr);
+    to_type = rr_graph.node_type(to_rr);
+    to_xlow = rr_graph.node_xlow(to_rr);
+    to_ylow = rr_graph.node_ylow(to_rr);
+    to_xhigh = rr_graph.node_xhigh(to_rr);
+    to_yhigh = rr_graph.node_yhigh(to_rr);
+    to_ptc = rr_graph.node_ptc_num(to_rr);
 
     switch (from_type) {
         case SOURCE:
@@ -393,8 +395,8 @@ static bool check_adjacent(int from_node, int to_node) {
             if (to_type == IPIN) {
                 num_adj += 1; //adjacent
             } else if (to_type == CHANX) {
-                from_xhigh = rr_graph.node_xhigh(RRNodeId(from_node));
-                to_xhigh = rr_graph.node_xhigh(RRNodeId(to_node));
+                from_xhigh = rr_graph.node_xhigh(from_rr);
+                to_xhigh = rr_graph.node_xhigh(to_rr);
                 if (from_ylow == to_ylow) {
                     /* UDSD Modification by WMF Begin */
                     /*For Fs > 3, can connect to overlapping wire segment */
@@ -426,8 +428,8 @@ static bool check_adjacent(int from_node, int to_node) {
             if (to_type == IPIN) {
                 num_adj += 1; //adjacent
             } else if (to_type == CHANY) {
-                from_yhigh = rr_graph.node_yhigh(RRNodeId(from_node));
-                to_yhigh = rr_graph.node_yhigh(RRNodeId(to_node));
+                from_yhigh = rr_graph.node_yhigh(from_rr);
+                to_yhigh = rr_graph.node_yhigh(to_rr);
                 if (from_xlow == to_xlow) {
                     /* UDSD Modification by WMF Begin */
                     if (to_yhigh == from_ylow - 1 || from_yhigh == to_ylow - 1) {
@@ -572,7 +574,7 @@ static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_
                                     size_t(blk_id), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), iclass, inode, rr_type);
                 }
 
-                ipin = device_ctx.rr_nodes[inode].ptc_num();
+                ipin = rr_graph.node_pin_num(RRNodeId(inode));
                 if (physical_tile_type(blk_id)->pin_class[ipin] != iclass) {
                     VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                                     "in check_locally_used_opins: block #%lu (%s):\n"

vpr/src/route/check_rr_graph.cpp

@@ -237,7 +237,7 @@ void check_rr_graph(const t_graph_type graph_type,
                     if (rr_graph.node_type(rr_node) == IPIN || rr_graph.node_type(rr_node) == OPIN) {
                         if (has_adjacent_channel(node, device_ctx.grid)) {
                             auto block_type = device_ctx.grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)].type;
-                            std::string pin_name = block_type_pin_index_to_name(block_type, node.pin_num());
+                            std::string pin_name = block_type_pin_index_to_name(block_type, rr_graph.node_pin_num(rr_node));
                             /* Print error messages for all the sides that a node may appear */
                             for (const e_side& node_side : SIDES) {
                                 if (!rr_graph.is_node_on_specific_side(rr_node, node_side)) {
@@ -282,7 +282,7 @@ static bool rr_node_is_global_clb_ipin(RRNodeId inode) {
     if (rr_graph.node_type(inode) != IPIN)
         return (false);
 
-    ipin = device_ctx.rr_nodes[size_t(inode)].ptc_num();
+    ipin = rr_graph.node_pin_num(inode);
 
     return type->is_ignored_pin[ipin];
 }
@@ -306,7 +306,7 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext&
     xhigh = rr_graph.node_xhigh(rr_node);
     ylow = rr_graph.node_ylow(rr_node);
     yhigh = rr_graph.node_yhigh(rr_node);
-    ptc_num = device_ctx.rr_nodes[inode].ptc_num();
+    ptc_num = rr_graph.node_ptc_num(rr_node);
     capacity = rr_graph.node_capacity(rr_node);
     cost_index = rr_graph.node_cost_index(rr_node);
     type = nullptr;