|
| 1 | +## Uses of xlow, xhigh, ylow, yhigh |
| 2 | + |
| 3 | +| Function | Use Scenario | One Usage (Location) | Count | |
| 4 | +| -- | -- | -- | -- | |
| 5 | +| xlow | retrieve physical tile from device_ctx.grid | test_fasm.cpp:193 | 16 | |
| 6 | +| xlow | Obtain length of wire | stats.cpp:313 | 3 | |
| 7 | +| xlow | Determine switchpoint | draw.cpp:1475 | 1 | |
| 8 | +| xlow | Draw from one edge to the other | draw.cpp:1934 | 1 | |
| 9 | +| xlow | Create bounding box | draw.cpp:2083 | 1 | |
| 10 | +| xlow | Check if nodes are adjacent | check_route.cpp:481 | 1 | |
| 11 | +| xlow | Check if node is initialized | check_route.cpp:64 | 3 | |
| 12 | +| xlow | Include x value in console output | check_route.cpp:258 | 5 | |
| 13 | +| xlow | Create a serial num for the wire x value in console output | check_route.cpp:198 | 3 | |
| 14 | +| xlow | Count cblocks | rr_graph_area.cpp:229 | 3 | |
| 15 | +| xlow | Return the segment number (distance along the channel) of the connection box from from_rr_type (CHANX or CHANY) to to_node (IPIN) | rr_graph_util.cpp:21 | 1 | |
| 16 | +| xlow | Check direction going from one node to another| rr_graph_util.cpp:45 | 1 | |
| 17 | +| xlow | Write Coordinates | VprTimingGraphResolver.cpp:345 | 1 | |
| 18 | +<br><br><br> |
| 19 | + |
| 20 | +## Retrieve Physical Tile from device_ctx.grid |
| 21 | +```cpp |
| 22 | +static std::string get_pin_feature (size_t inode) { |
| 23 | + auto& device_ctx = g_vpr_ctx.device(); |
| 24 | + |
| 25 | + // Get tile physical tile and the pin number |
| 26 | + int ilow = device_ctx.rr_nodes[inode].xlow(); // <----------------------------- Use of xlow() |
| 27 | + int jlow = device_ctx.rr_nodes[inode].ylow(); |
| 28 | + auto physical_tile = device_ctx.grid[ilow][jlow].type; |
| 29 | + int pin_num = device_ctx.rr_nodes[inode].ptc_num(); |
| 30 | + |
| 31 | + // Get the sub tile (type, not instance) and index of its pin that matches |
| 32 | + // the node index. |
| 33 | + const t_sub_tile* sub_tile_type = nullptr; |
| 34 | + int sub_tile_pin = -1; |
| 35 | + |
| 36 | + for (auto& sub_tile : physical_tile->sub_tiles) { |
| 37 | + auto max_inst_pins = sub_tile.num_phy_pins / sub_tile.capacity.total(); |
| 38 | + for (int pin = 0; pin < sub_tile.num_phy_pins; pin++) { |
| 39 | + if (sub_tile.sub_tile_to_tile_pin_indices[pin] == pin_num) { |
| 40 | + sub_tile_type = &sub_tile; |
| 41 | + sub_tile_pin = pin % max_inst_pins; |
| 42 | + break; |
| 43 | + } |
| 44 | + } |
| 45 | + |
| 46 | + if (sub_tile_type != nullptr) { |
| 47 | + break; |
| 48 | + } |
| 49 | + } |
| 50 | +``` |
| 51 | +
|
| 52 | +<br><br><br> |
| 53 | +
|
| 54 | +## Obtain length of wire |
| 55 | +```cpp |
| 56 | +while (tptr != nullptr) { |
| 57 | + inode = tptr->index; |
| 58 | + curr_type = device_ctx.rr_nodes[inode].type(); |
| 59 | +
|
| 60 | + if (curr_type == SINK) { /* Starting a new segment */ |
| 61 | + tptr = tptr->next; /* Link to existing path - don't add to len. */ |
| 62 | + if (tptr == nullptr) |
| 63 | + break; |
| 64 | +
|
| 65 | + curr_type = device_ctx.rr_nodes[tptr->index].type(); |
| 66 | + } |
| 67 | +
|
| 68 | + else if (curr_type == CHANX || curr_type == CHANY) { |
| 69 | + segments++; |
| 70 | + length += 1 + device_ctx.rr_nodes[inode].xhigh() - device_ctx.rr_nodes[inode].xlow() // <----------------------------- Use of xlow() |
| 71 | + + device_ctx.rr_nodes[inode].yhigh() - device_ctx.rr_nodes[inode].ylow(); |
| 72 | +
|
| 73 | + if (curr_type != prev_type && (prev_type == CHANX || prev_type == CHANY)) |
| 74 | + bends++; |
| 75 | + } |
| 76 | +
|
| 77 | + prev_type = curr_type; |
| 78 | + tptr = tptr->next; |
| 79 | + } |
| 80 | +
|
| 81 | + *bends_ptr = bends; |
| 82 | + *len_ptr = length; |
| 83 | + *segments_ptr = segments; |
| 84 | +} |
| 85 | +``` |
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