Merge pull request #2066 from verilog-to-routing/flat_routing

Add Intra-Cluster Pins & Connections to RR Graph

Author: vaughnbetz

libs/libarchfpga/src/physical_types.h

@@ -450,6 +450,10 @@ struct t_class {
 struct t_class_range {
     int low = 0;
     int high = 0;
+    // Returns the total number of classes
+    int total_num() const {
+        return high - low + 1;
+    }
 };
 
 enum e_power_wire_type {
@@ -613,11 +617,14 @@ struct t_physical_tile_type {
 
     std::vector<t_class> class_inf; /* [0..num_class-1] */
 
+    std::unordered_map<int, t_class> internal_class_inf;
+
     std::vector<int> pin_width_offset;  // [0..num_pins-1]
     std::vector<int> pin_height_offset; // [0..num_pins-1]
     std::vector<int> pin_class;         // [0..num_pins-1]
-    std::vector<bool> is_ignored_pin;   // [0..num_pins-1]
-    std::vector<bool> is_pin_global;    // [0..num_pins-1]
+    std::unordered_map<int, int> internal_pin_class;
+    std::vector<bool> is_ignored_pin; // [0..num_pins-1]
+    std::vector<bool> is_pin_global;  // [0..num_pins-1]
 
     std::vector<t_fc_specification> fc_specs;
 
@@ -725,6 +732,9 @@ struct t_sub_tile {
                                ///>      indices ranging from 4 to 7.
     t_class_range class_range;
 
+    std::vector<std::unordered_map<t_logical_block_type_ptr, int>> starting_internal_class_idx;
+    std::vector<std::unordered_map<t_logical_block_type_ptr, int>> starting_internal_pin_idx;
+
     int num_phy_pins = 0;
 
     int index = -1;
@@ -818,6 +828,15 @@ struct t_physical_tile_port {
  * index: Keep track of type in array for easy access
  * physical_tile_index: index of the corresponding physical tile type
  *
+ * pin_logical_num_to_pb_pin_mapping: Contains all the pins, including pins on the root-level block and internal pins, in
+ * the logical block. The key of this map is the logical number of the pin, and the value is a pointer to the
+ * corresponding pb_graph_pin
+ *
+ * pb_pin_to_class_logical_num_mapping: Maps each pin to its corresponding class's logical number. To retrieve the actual class, use this number as an
+ * index to logical_class_inf.
+ *
+ * logical_class_inf: Contains all the classes inside the logical block. The index of each class is the logical number associate with the class.
+ *
  * A logical block is the implementation of a component's functionality of the FPGA device
  * and it identifies its logical behaviour and internal connections.
  *
@@ -840,6 +859,10 @@ struct t_logical_block_type {
     std::vector<t_physical_tile_type_ptr> equivalent_tiles; ///>List of physical tiles at which one could
                                                             ///>place this type of netlist block.
 
+    std::unordered_map<int, const t_pb_graph_pin*> pin_logical_num_to_pb_pin_mapping;   /* pin_logical_num_to_pb_pin_mapping[pin logical number] -> pb_graph_pin ptr} */
+    std::unordered_map<const t_pb_graph_pin*, int> pb_pin_to_class_logical_num_mapping; /* pb_pin_to_class_logical_num_mapping[pb_graph_pin ptr] -> class logical number */
+    std::vector<t_class> logical_class_inf;                                             /* logical_class_inf[class_logical_number] -> class */
+
     // Is this t_logical_block_type empty?
     bool is_empty() const;
 };

libs/libarchfpga/src/physical_types_util.cpp

@@ -160,7 +160,8 @@ int get_physical_pin_from_capacity_location(t_physical_tile_type_ptr physical_ti
 std::pair<int, int> get_capacity_location_from_physical_pin(t_physical_tile_type_ptr physical_tile, int pin);
 
 ///@brief Returns the name of the pin_index'th pin on the specified block type
-std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_index);
+// #TODO: is_flat shouldn't have a default value - This should be modified ASAP!
+std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_physical_num, bool is_flat = false);
 
 ///@brief Returns the name of the class_index'th pin class on the specified block type
 std::vector<std::string> block_type_class_index_to_pin_names(t_physical_tile_type_ptr type, int class_index);
@@ -301,4 +302,80 @@ const t_physical_tile_port* get_port_by_pin(const t_sub_tile* sub_tile, int pin)
  */
 const t_port* get_port_by_pin(t_logical_block_type_ptr type, int pin);
 
+/************************************ Access to intra-block resources ************************************/
+
+/* Access information related to pin classes */
+
+/** get information given class physical num **/
+std::tuple<const t_sub_tile*, int> get_sub_tile_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int physical_class_num);
+
+t_logical_block_type_ptr get_logical_block_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int physical_class_num);
+
+std::vector<int> get_pin_list_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num);
+
+PortEquivalence get_port_equivalency_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num);
+
+e_pin_type get_class_type_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num);
+
+int get_class_num_pins_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num);
+
+int get_pin_physical_num_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int physical_class_num, int pin_logical_num);
+
+bool is_class_on_tile(t_physical_tile_type_ptr physical_tile, int class_physical_num);
+/** **/
+
+/** get classes under different blocks **/
+std::unordered_map<int, const t_class*> get_pb_graph_node_num_class_pairs(t_physical_tile_type_ptr physical_tile,
+                                                                          const t_sub_tile* sub_tile,
+                                                                          t_logical_block_type_ptr logical_block,
+                                                                          int sub_tile_relative_cap,
+                                                                          const t_pb_graph_node* pb_graph_node);
+/** **/
+int get_total_num_sub_tile_internal_classes(const t_sub_tile* sub_tile);
+
+int get_total_num_tile_internal_classes(t_physical_tile_type_ptr physical_tile);
+
+int get_tile_class_max_ptc(t_physical_tile_type_ptr tile, bool is_flat);
+
+/*  */
+
+/* Access information related to pins */
+
+/** get information given pin physical number **/
+std::tuple<const t_sub_tile*, int> get_sub_tile_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int physical_num);
+
+t_logical_block_type_ptr get_logical_block_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int physical_num);
+
+const t_pb_graph_pin* get_pb_pin_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int physical_num);
+
+PortEquivalence get_port_equivalency_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int pin_physical_num);
+
+e_pin_type get_pin_type_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int physical_num);
+
+int get_class_num_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int pin_physical_num);
+
+bool is_pin_on_tile(t_physical_tile_type_ptr physical_tile, int physical_num);
+
+std::vector<int> get_pb_graph_node_pins(const t_sub_tile* sub_tile,
+                                        t_logical_block_type_ptr logical_block,
+                                        int relative_cap,
+                                        const t_pb_graph_node* pb_graph_node);
+
+std::vector<int> get_physical_pin_driving_pins(t_physical_tile_type_ptr physical_type,
+                                               t_logical_block_type_ptr logical_block,
+                                               int pin_physical_num);
+
+int get_pb_pin_physical_num(const t_sub_tile* sub_tile,
+                            t_logical_block_type_ptr logical_block,
+                            int relative_cap,
+                            const t_pb_graph_pin* pin);
+
+int get_total_num_sub_tile_internal_pins(const t_sub_tile* sub_tile);
+
+int get_total_num_tile_internal_pins(t_physical_tile_type_ptr tile);
+
+int get_tile_ipin_opin_max_ptc(t_physical_tile_type_ptr tile, bool is_flat);
+
+/* */
+
 #endif

libs/libarchfpga/src/physical_types_util.h

@@ -534,12 +534,12 @@ static void LoadPinLoc(pugi::xml_node Locations,
         std::vector<int> input_pins;
         std::vector<int> output_pins;
         for (int pin_num = 0; pin_num < type->num_pins; ++pin_num) {
-            int iclass = type->pin_class[pin_num];
+            auto class_type = get_pin_type_from_pin_physical_num(type, pin_num);
 
-            if (type->class_inf[iclass].type == RECEIVER) {
+            if (class_type == RECEIVER) {
                 input_pins.push_back(pin_num);
             } else {
-                VTR_ASSERT(type->class_inf[iclass].type == DRIVER);
+                VTR_ASSERT(class_type == DRIVER);
                 output_pins.push_back(pin_num);
             }
         }