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Merged
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Dec 13, 2019
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Update STM32F4xx Drivers and CMSIS #831

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dda963e
[F4] Update STM32F4xx HAL Drivers to v1.7.7
fpistm Dec 13, 2019
2660d9f
[F4] Update STM32F4xx CMSIS to v1.7.7
fpistm Dec 13, 2019
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4 changes: 0 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -8408,10 +8408,6 @@ typedef struct
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM9))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/********************** TIM Instances : 32 bit Counter ************************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
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4 changes: 0 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h
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Expand Up @@ -8408,10 +8408,6 @@ typedef struct
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM9))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/********************** TIM Instances : 32 bit Counter ************************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
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4 changes: 0 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h
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Expand Up @@ -14004,10 +14004,6 @@ typedef struct
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM9) || \
((INSTANCE) == TIM12))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/********************** TIM Instances : 32 bit Counter ************************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
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8 changes: 2 additions & 6 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h
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Expand Up @@ -13576,7 +13576,7 @@ typedef struct
#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
#define ETH_DMASR_TPS_Suspended_Pos (21U)
#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
#define ETH_DMASR_TPS_Closing_Pos (20U)
#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
Expand All @@ -13598,7 +13598,7 @@ typedef struct
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
#define ETH_DMASR_RPS_Queuing_Pos (17U)
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
#define ETH_DMASR_NIS_Pos (16U)
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
Expand Down Expand Up @@ -15295,10 +15295,6 @@ typedef struct
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM9) || \
((INSTANCE) == TIM12))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/********************** TIM Instances : 32 bit Counter ************************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
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3 changes: 0 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h
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Expand Up @@ -7132,9 +7132,6 @@ typedef struct
((INSTANCE) == TIM9) || \
((INSTANCE) == TIM11))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM5) || \
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3 changes: 0 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h
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Expand Up @@ -7136,9 +7136,6 @@ typedef struct
((INSTANCE) == TIM9) || \
((INSTANCE) == TIM11))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM5) || \
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3 changes: 0 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h
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Expand Up @@ -7080,9 +7080,6 @@ typedef struct
((INSTANCE) == TIM9) || \
((INSTANCE) == TIM11))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM5) || \
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4 changes: 0 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h
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Expand Up @@ -8443,10 +8443,6 @@ typedef struct
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM9))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/********************** TIM Instances : 32 bit Counter ************************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
Expand Down
5 changes: 0 additions & 5 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h
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Expand Up @@ -13117,9 +13117,6 @@ typedef struct
((INSTANCE) == TIM13)|| \
((INSTANCE) == TIM14))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
Expand Down Expand Up @@ -13461,8 +13458,6 @@ typedef struct
/***************************** FMPI2C Instances *******************************/
#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
#define IS_FMPSMBUS_ALL_INSTANCE IS_FMPI2C_ALL_INSTANCE
/****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
Expand Down
5 changes: 0 additions & 5 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h
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Expand Up @@ -14095,9 +14095,6 @@ typedef struct
((INSTANCE) == TIM13)|| \
((INSTANCE) == TIM14))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
Expand Down Expand Up @@ -14442,8 +14439,6 @@ typedef struct

/****************************** QSPI Instances ********************************/
#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
/****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
Expand Down
5 changes: 0 additions & 5 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412vx.h
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Expand Up @@ -14109,9 +14109,6 @@ typedef struct
((INSTANCE) == TIM13)|| \
((INSTANCE) == TIM14))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
Expand Down Expand Up @@ -14456,8 +14453,6 @@ typedef struct

/****************************** QSPI Instances ********************************/
#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
/****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
Expand Down
5 changes: 0 additions & 5 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412zx.h
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Expand Up @@ -14131,9 +14131,6 @@ typedef struct
((INSTANCE) == TIM13)|| \
((INSTANCE) == TIM14))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
Expand Down Expand Up @@ -14479,8 +14476,6 @@ typedef struct

/****************************** QSPI Instances ********************************/
#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
/****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
Expand Down
8 changes: 1 addition & 7 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h
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Expand Up @@ -6898,13 +6898,12 @@ typedef struct
#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER FLASH_CR_MER_Msk
#define FLASH_CR_SNB_Pos (3U)
#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
#define FLASH_CR_SNB_Msk (0x0FUL << FLASH_CR_SNB_Pos) /*!< 0x00000078 */
#define FLASH_CR_SNB FLASH_CR_SNB_Msk
#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
#define FLASH_CR_PSIZE_Pos (8U)
#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
Expand Down Expand Up @@ -15057,9 +15056,6 @@ typedef struct
((INSTANCE) == TIM13)|| \
((INSTANCE) == TIM14))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
Expand Down Expand Up @@ -15417,8 +15413,6 @@ typedef struct

/****************************** QSPI Instances ********************************/
#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
/****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
Expand Down
3 changes: 0 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f415xx.h
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Expand Up @@ -14184,9 +14184,6 @@ typedef struct
((INSTANCE) == TIM13)|| \
((INSTANCE) == TIM14))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
Expand Down
7 changes: 2 additions & 5 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h
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Expand Up @@ -13856,7 +13856,7 @@ typedef struct
#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
#define ETH_DMASR_TPS_Suspended_Pos (21U)
#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
#define ETH_DMASR_TPS_Closing_Pos (20U)
#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
Expand All @@ -13878,7 +13878,7 @@ typedef struct
#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
#define ETH_DMASR_RPS_Queuing_Pos (17U)
#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
#define ETH_DMASR_NIS_Pos (16U)
#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
Expand Down Expand Up @@ -15470,9 +15470,6 @@ typedef struct
((INSTANCE) == TIM13)|| \
((INSTANCE) == TIM14))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
Expand Down
8 changes: 1 addition & 7 deletions system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h
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Expand Up @@ -6934,13 +6934,12 @@ typedef struct
#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER FLASH_CR_MER_Msk
#define FLASH_CR_SNB_Pos (3U)
#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
#define FLASH_CR_SNB_Msk (0x0FUL << FLASH_CR_SNB_Pos) /*!< 0x00000078 */
#define FLASH_CR_SNB FLASH_CR_SNB_Msk
#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
#define FLASH_CR_PSIZE_Pos (8U)
#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
Expand Down Expand Up @@ -15210,9 +15209,6 @@ typedef struct
((INSTANCE) == TIM13)|| \
((INSTANCE) == TIM14))

/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)

/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
Expand Down Expand Up @@ -15570,8 +15566,6 @@ typedef struct

/****************************** QSPI Instances ********************************/
#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
/****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
Expand Down
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