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Update L4 HAL and CMSIS Drivers to the latest version #321

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Sep 19, 2018
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3 changes: 3 additions & 0 deletions cores/arduino/stm32/HAL/stm32yyxx_hal_exti.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
#ifdef STM32L4xx
#include "stm32l4xx_hal_exti.c"
#endif
4 changes: 4 additions & 0 deletions cores/arduino/stm32/stm32_def_build.h
Original file line number Diff line number Diff line change
Expand Up @@ -247,6 +247,10 @@
#define CMSIS_STARTUP_FILE "startup_stm32l162xdx.s"
#elif defined(STM32L162xE)
#define CMSIS_STARTUP_FILE "startup_stm32l162xe.s"
#elif defined(STM32L412xx)
#define CMSIS_STARTUP_FILE "startup_stm32l412xx.s"
#elif defined(STM32L422xx)
#define CMSIS_STARTUP_FILE "startup_stm32l422xx.s"
#elif defined(STM32L431xx)
#define CMSIS_STARTUP_FILE "startup_stm32l431xx.s"
#elif defined(STM32L432xx)
Expand Down
10,907 changes: 10,907 additions & 0 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h

Large diffs are not rendered by default.

11,135 changes: 11,135 additions & 0 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h

Large diffs are not rendered by default.

11 changes: 7 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h
Original file line number Diff line number Diff line change
Expand Up @@ -711,7 +711,6 @@ typedef struct
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
} RTC_TypeDef;


/**
* @brief Serial Audio Interface
*/
Expand Down Expand Up @@ -5672,7 +5671,7 @@ typedef struct

/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */

/******************** Bit definition for CRC_CR register ********************/
Expand Down Expand Up @@ -7035,15 +7034,15 @@ typedef struct
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk

/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk


Expand Down Expand Up @@ -9162,6 +9161,8 @@ typedef struct
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
*/
#define RCC_PLLSAI1_SUPPORT
#define RCC_PLLP_SUPPORT
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
Expand Down Expand Up @@ -15039,12 +15040,14 @@ typedef struct
/******************************************************************************/

/* Aliases for __IRQn */
#define TIM6_IRQn TIM6_DAC_IRQn
#define ADC1_2_IRQn ADC1_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define HASH_RNG_IRQn RNG_IRQn
#define HASH_CRS_IRQn CRS_IRQn

/* Aliases for __IRQHandler */
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
#define ADC1_2_IRQHandler ADC1_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define HASH_RNG_IRQHandler RNG_IRQHandler
Expand Down
11 changes: 7 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h
Original file line number Diff line number Diff line change
Expand Up @@ -707,7 +707,6 @@ typedef struct
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
} RTC_TypeDef;


/**
* @brief Serial Audio Interface
*/
Expand Down Expand Up @@ -5657,7 +5656,7 @@ typedef struct

/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */

/******************** Bit definition for CRC_CR register ********************/
Expand Down Expand Up @@ -7038,15 +7037,15 @@ typedef struct
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk

/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk


Expand Down Expand Up @@ -8820,6 +8819,8 @@ typedef struct
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
*/
#define RCC_PLLSAI1_SUPPORT
#define RCC_PLLP_SUPPORT
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
Expand Down Expand Up @@ -14828,13 +14829,15 @@ typedef struct
/******************************************************************************/

/* Aliases for __IRQn */
#define TIM6_IRQn TIM6_DAC_IRQn
#define ADC1_2_IRQn ADC1_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define HASH_RNG_IRQn RNG_IRQn
#define HASH_CRS_IRQn CRS_IRQn
#define USB_FS_IRQn USB_IRQn

/* Aliases for __IRQHandler */
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
#define ADC1_2_IRQHandler ADC1_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define HASH_RNG_IRQHandler RNG_IRQHandler
Expand Down
11 changes: 7 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h
Original file line number Diff line number Diff line change
Expand Up @@ -727,7 +727,6 @@ typedef struct
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
} RTC_TypeDef;


/**
* @brief Serial Audio Interface
*/
Expand Down Expand Up @@ -5731,7 +5730,7 @@ typedef struct

/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */

/******************** Bit definition for CRC_CR register ********************/
Expand Down Expand Up @@ -7118,15 +7117,15 @@ typedef struct
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk

/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk


Expand Down Expand Up @@ -9254,6 +9253,8 @@ typedef struct
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
*/
#define RCC_PLLSAI1_SUPPORT
#define RCC_PLLP_SUPPORT
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
Expand Down Expand Up @@ -15935,13 +15936,15 @@ typedef struct
/******************************************************************************/

/* Aliases for __IRQn */
#define TIM6_IRQn TIM6_DAC_IRQn
#define ADC1_2_IRQn ADC1_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define HASH_RNG_IRQn RNG_IRQn
#define HASH_CRS_IRQn CRS_IRQn
#define USB_FS_IRQn USB_IRQn

/* Aliases for __IRQHandler */
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
#define ADC1_2_IRQHandler ADC1_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define HASH_RNG_IRQHandler RNG_IRQHandler
Expand Down
11 changes: 7 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h
Original file line number Diff line number Diff line change
Expand Up @@ -708,7 +708,6 @@ typedef struct
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
} RTC_TypeDef;


/**
* @brief Serial Audio Interface
*/
Expand Down Expand Up @@ -5692,7 +5691,7 @@ typedef struct

/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */

/******************** Bit definition for CRC_CR register ********************/
Expand Down Expand Up @@ -7254,15 +7253,15 @@ typedef struct
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk

/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk


Expand Down Expand Up @@ -9036,6 +9035,8 @@ typedef struct
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
*/
#define RCC_PLLSAI1_SUPPORT
#define RCC_PLLP_SUPPORT
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
Expand Down Expand Up @@ -15056,13 +15057,15 @@ typedef struct
/******************************************************************************/

/* Aliases for __IRQn */
#define TIM6_IRQn TIM6_DAC_IRQn
#define ADC1_2_IRQn ADC1_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define HASH_RNG_IRQn RNG_IRQn
#define HASH_CRS_IRQn CRS_IRQn
#define USB_FS_IRQn USB_IRQn

/* Aliases for __IRQHandler */
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
#define ADC1_2_IRQHandler ADC1_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define HASH_RNG_IRQHandler RNG_IRQHandler
Expand Down
11 changes: 7 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h
Original file line number Diff line number Diff line change
Expand Up @@ -728,7 +728,6 @@ typedef struct
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
} RTC_TypeDef;


/**
* @brief Serial Audio Interface
*/
Expand Down Expand Up @@ -5766,7 +5765,7 @@ typedef struct

/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */

/******************** Bit definition for CRC_CR register ********************/
Expand Down Expand Up @@ -7334,15 +7333,15 @@ typedef struct
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk

/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk


Expand Down Expand Up @@ -9470,6 +9469,8 @@ typedef struct
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
*/
#define RCC_PLLSAI1_SUPPORT
#define RCC_PLLP_SUPPORT
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
Expand Down Expand Up @@ -16163,13 +16164,15 @@ typedef struct
/******************************************************************************/

/* Aliases for __IRQn */
#define TIM6_IRQn TIM6_DAC_IRQn
#define ADC1_2_IRQn ADC1_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define HASH_RNG_IRQn RNG_IRQn
#define HASH_CRS_IRQn CRS_IRQn
#define USB_FS_IRQn USB_IRQn

/* Aliases for __IRQHandler */
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
#define ADC1_2_IRQHandler ADC1_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define HASH_RNG_IRQHandler RNG_IRQHandler
Expand Down
11 changes: 7 additions & 4 deletions system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h
Original file line number Diff line number Diff line change
Expand Up @@ -750,7 +750,6 @@ typedef struct
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
} RTC_TypeDef;


/**
* @brief Serial Audio Interface
*/
Expand Down Expand Up @@ -5722,7 +5721,7 @@ typedef struct

/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */

/******************** Bit definition for CRC_CR register ********************/
Expand Down Expand Up @@ -7292,15 +7291,15 @@ typedef struct
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk

/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk


Expand Down Expand Up @@ -9413,6 +9412,8 @@ typedef struct
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
*/
#define RCC_PLLSAI1_SUPPORT
#define RCC_PLLP_SUPPORT
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
Expand Down Expand Up @@ -15296,6 +15297,7 @@ typedef struct
/******************************************************************************/

/* Aliases for __IRQn */
#define TIM6_IRQn TIM6_DAC_IRQn
#define ADC1_2_IRQn ADC1_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define HASH_RNG_IRQn RNG_IRQn
Expand All @@ -15304,6 +15306,7 @@ typedef struct
#define DFSDM1_IRQn DFSDM1_FLT1_IRQn

/* Aliases for __IRQHandler */
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
#define ADC1_2_IRQHandler ADC1_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define HASH_RNG_IRQHandler RNG_IRQHandler
Expand Down
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