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Merged
merged 4 commits into from
Mar 5, 2025
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chore(h5): update to latest STM32CubeH5 v1.5.0 #2671

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17f3be3
system(H5) update STM32H5xx HAL Drivers to v1.5.0
fpistm Mar 4, 2025
1f77ad9
system(H5): update STM32H5xx CMSIS Drivers to v1.4.0
fpistm Mar 4, 2025
c93f1c5
core(H5): update wrapped files
fpistm Mar 4, 2025
0852096
system(h5): update STM32H5xx hal default config
fpistm Mar 4, 2025
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4 changes: 3 additions & 1 deletion libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,9 @@
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-parameter"

#ifdef STM32H7xx
#ifdef STM32H5xx
#include "stm32h5xx_hal_sdio.c"
#elif STM32H7xx
#include "stm32h7xx_hal_sdio.c"
#elif STM32U5xx
#include "stm32u5xx_hal_sdio.c"
Expand Down
11 changes: 3 additions & 8 deletions system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -210,11 +210,6 @@ typedef struct
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
uint32_t RESERVED3[246]; /*!< Reserved, */
__IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */
__IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */
} CRC_TypeDef;

/**
Expand Down Expand Up @@ -2480,7 +2475,7 @@ typedef struct
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */

/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
Expand Down Expand Up @@ -6456,7 +6451,7 @@ typedef struct
#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */
#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk
#define GPIO_HSLVR_HSLV11_Pos (11U)
#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
#define GPIO_HSLVR_HSLV11_Msk (0x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk
#define GPIO_HSLVR_HSLV12_Pos (12U)
#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */
Expand Down Expand Up @@ -6506,7 +6501,7 @@ typedef struct
#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */
#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk
#define GPIO_SECCFGR_SEC11_Pos (11U)
#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
#define GPIO_SECCFGR_SEC11_Msk (0x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk
#define GPIO_SECCFGR_SEC12_Pos (12U)
#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */
Expand Down
31 changes: 21 additions & 10 deletions system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h523xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -239,11 +239,6 @@ typedef struct
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
uint32_t RESERVED3[246]; /*!< Reserved, */
__IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */
__IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */
} CRC_TypeDef;

/**
Expand Down Expand Up @@ -814,6 +809,8 @@ typedef struct

typedef XSPI_TypeDef OCTOSPI_TypeDef;



/**
* @brief Power Control
*/
Expand Down Expand Up @@ -3706,7 +3703,7 @@ typedef struct
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */

/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
Expand Down Expand Up @@ -3896,7 +3893,6 @@ typedef struct
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */



/******************************************************************************/
/* */
/* CRC calculation unit */
Expand Down Expand Up @@ -8001,6 +7997,7 @@ typedef struct
#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */


/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
Expand Down Expand Up @@ -8754,7 +8751,7 @@ typedef struct
#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */
#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk
#define GPIO_HSLVR_HSLV11_Pos (11U)
#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
#define GPIO_HSLVR_HSLV11_Msk (0x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk
#define GPIO_HSLVR_HSLV12_Pos (12U)
#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */
Expand Down Expand Up @@ -8804,7 +8801,7 @@ typedef struct
#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */
#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk
#define GPIO_SECCFGR_SEC11_Pos (11U)
#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
#define GPIO_SECCFGR_SEC11_Msk (0x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk
#define GPIO_SECCFGR_SEC12_Pos (12U)
#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */
Expand Down Expand Up @@ -13477,6 +13474,9 @@ typedef struct
#define RCC_AHB2LPENR_RNGLPEN_Pos (18U)
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
#define RCC_AHB2LPENR_PKALPEN_Pos (19U)
#define RCC_AHB2LPENR_PKALPEN_Msk (0x1UL << RCC_AHB2LPENR_PKALPEN_Pos) /*!< 0x00080000 */
#define RCC_AHB2LPENR_PKALPEN RCC_AHB2LPENR_PKALPEN_Msk
#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
Expand Down Expand Up @@ -15830,6 +15830,8 @@ typedef struct
#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos)
#define GTZC_CFGR3_RNG_Pos (18U)
#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos)
#define GTZC_CFGR3_PKA_Pos (20U)
#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos)
#define GTZC_CFGR3_SDMMC1_Pos (21U)
#define GTZC_CFGR3_SDMMC1_Msk (0x01UL << GTZC_CFGR3_SDMMC1_Pos)
#define GTZC_CFGR3_FMC_REG_Pos (23U)
Expand Down Expand Up @@ -15981,6 +15983,8 @@ typedef struct
#define GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk
#define GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos
#define GTZC_TZSC1_SECCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk
#define GTZC_TZSC1_SECCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos
#define GTZC_TZSC1_SECCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk
#define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos
#define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk
#define GTZC_TZSC1_SECCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos
Expand Down Expand Up @@ -16088,6 +16092,8 @@ typedef struct
#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk
#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos
#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk
#define GTZC_TZSC1_PRIVCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos
#define GTZC_TZSC1_PRIVCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk
#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos
#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk
#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos
Expand Down Expand Up @@ -16194,6 +16200,8 @@ typedef struct
#define GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk
#define GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos
#define GTZC_TZIC1_IER3_RNG_Msk GTZC_CFGR3_RNG_Msk
#define GTZC_TZIC1_IER3_PKA_Pos GTZC_CFGR3_PKA_Pos
#define GTZC_TZIC1_IER3_PKA_Msk GTZC_CFGR3_PKA_Msk
#define GTZC_TZIC1_IER3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos
#define GTZC_TZIC1_IER3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk
#define GTZC_TZIC1_IER3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos
Expand Down Expand Up @@ -16344,6 +16352,8 @@ typedef struct
#define GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk
#define GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos
#define GTZC_TZIC1_SR3_RNG_Msk GTZC_CFGR3_RNG_Msk
#define GTZC_TZIC1_SR3_PKA_Pos GTZC_CFGR3_PKA_Pos
#define GTZC_TZIC1_SR3_PKA_Msk GTZC_CFGR3_PKA_Msk
#define GTZC_TZIC1_SR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos
#define GTZC_TZIC1_SR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk
#define GTZC_TZIC1_SR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos
Expand Down Expand Up @@ -16494,6 +16504,8 @@ typedef struct
#define GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk
#define GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos
#define GTZC_TZIC1_FCR3_RNG_Msk GTZC_CFGR3_RNG_Msk
#define GTZC_TZIC1_FCR3_PKA_Pos GTZC_CFGR3_PKA_Pos
#define GTZC_TZIC1_FCR3_PKA_Msk GTZC_CFGR3_PKA_Msk
#define GTZC_TZIC1_FCR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos
#define GTZC_TZIC1_FCR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk
#define GTZC_TZIC1_FCR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos
Expand Down Expand Up @@ -20161,7 +20173,6 @@ typedef struct

/******************************* USB DRD FS PCD Instances *************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S))

/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */

/** @} */ /* End of group STM32H523xx */
Expand Down
11 changes: 3 additions & 8 deletions system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h
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Expand Up @@ -242,11 +242,6 @@ typedef struct
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
uint32_t RESERVED3[246]; /*!< Reserved, */
__IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */
__IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */
} CRC_TypeDef;

/**
Expand Down Expand Up @@ -3865,7 +3860,7 @@ typedef struct
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */

/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
Expand Down Expand Up @@ -9163,7 +9158,7 @@ typedef struct
#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */
#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk
#define GPIO_HSLVR_HSLV11_Pos (11U)
#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
#define GPIO_HSLVR_HSLV11_Msk (0x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk
#define GPIO_HSLVR_HSLV12_Pos (12U)
#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */
Expand Down Expand Up @@ -9213,7 +9208,7 @@ typedef struct
#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */
#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk
#define GPIO_SECCFGR_SEC11_Pos (11U)
#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
#define GPIO_SECCFGR_SEC11_Msk (0x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk
#define GPIO_SECCFGR_SEC12_Pos (12U)
#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */
Expand Down
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