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Merged
merged 9 commits into from
Jan 25, 2018
Merged

Update HAL and CMSIS Drivers to the latest version #205

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2d70fc9
Updated STM32L1xx CMSIS to v2.2.3
fpistm Jan 23, 2018
e99cb17
Updated STM32L4xx CMSIS to v1.4.2
fpistm Jan 23, 2018
1286dc6
Updated STM32L4xx HAL Drivers to v1.8.2
fpistm Jan 23, 2018
d9bc3d4
Updated stm32l4xx_hal_conf.h in variant
fpistm Jan 24, 2018
9cc074f
Updated STM32F4xx HAL Drivers to v1.7.3
fpistm Jan 24, 2018
42d9759
Updated stm32f4xx_hal_conf.h in variant
fpistm Jan 24, 2018
b85eaad
Updated STM32F7xx HAL Drivers to v1.2.4
fpistm Jan 24, 2018
0921160
Updated STM32F7xx CMSIS to v1.2.2
fpistm Jan 24, 2018
8726db2
Updated stm32f7xx_hal_conf.h in variant
fpistm Jan 24, 2018
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47 changes: 34 additions & 13 deletions system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -14634,16 +14634,22 @@ typedef struct
#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */

/******************** Bit definition for USBPHYC_PLL register ********************/
#define USB_HS_PHYC_PLL_PLLEN_Pos (0U)
#define USB_HS_PHYC_PLL_PLLEN_Msk (0x1U << USB_HS_PHYC_PLL_PLLEN_Pos) /*!< 0x00000001 */
#define USB_HS_PHYC_PLL_PLLEN USB_HS_PHYC_PLL_PLLEN_Msk /*!< Enable PLL */
#define USB_HS_PHYC_PLL_PLLSEL_Pos (2U)
#define USB_HS_PHYC_PLL_PLLSEL_Msk (0x5U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000014 */
#define USB_HS_PHYC_PLL_PLLSEL USB_HS_PHYC_PLL_PLLSEL_Msk /*!< Controls PHY frequency operation selection */
#define USB_HS_PHYC_PLL_PLLSEL_1 (0x0U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000002 */
#define USB_HS_PHYC_PLL_PLLSEL_2 (0x1U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000004 */
#define USB_HS_PHYC_PLL_PLLSEL_3 (0x2U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000008 */
/******************** Bit definition for USBPHYC_PLL1 register ********************/
#define USB_HS_PHYC_PLL1_PLLEN_Pos (0U)
#define USB_HS_PHYC_PLL1_PLLEN_Msk (0x1U << USB_HS_PHYC_PLL1_PLLEN_Pos) /*!< 0x00000001 */
#define USB_HS_PHYC_PLL1_PLLEN USB_HS_PHYC_PLL1_PLLEN_Msk /*!< Enable PLL */
#define USB_HS_PHYC_PLL1_PLLSEL_Pos (1U)
#define USB_HS_PHYC_PLL1_PLLSEL_Msk (0x7U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x0000000E */
#define USB_HS_PHYC_PLL1_PLLSEL USB_HS_PHYC_PLL1_PLLSEL_Msk /*!< Controls PHY frequency operation selection */
#define USB_HS_PHYC_PLL1_PLLSEL_1 (0x1U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000002 */
#define USB_HS_PHYC_PLL1_PLLSEL_2 (0x2U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000004 */
#define USB_HS_PHYC_PLL1_PLLSEL_3 (0x4U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000008 */

#define USB_HS_PHYC_PLL1_PLLSEL_12MHZ 0x00000000U /*!< PHY PLL1 input clock frequency 12 MHz */
#define USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ USB_HS_PHYC_PLL1_PLLSEL_1 /*!< PHY PLL1 input clock frequency 12.5 MHz */
#define USB_HS_PHYC_PLL1_PLLSEL_16MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_1 | USB_HS_PHYC_PLL1_PLLSEL_2) /*!< PHY PLL1 input clock frequency 16 MHz */
#define USB_HS_PHYC_PLL1_PLLSEL_24MHZ USB_HS_PHYC_PLL1_PLLSEL_3 /*!< PHY PLL1 input clock frequency 24 MHz */
#define USB_HS_PHYC_PLL1_PLLSEL_25MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_2 | USB_HS_PHYC_PLL1_PLLSEL_3) /*!< PHY PLL1 input clock frequency 25 MHz */

/******************** Bit definition for USBPHYC_LDO register ********************/
#define USB_HS_PHYC_LDO_USED_Pos (0U)
Expand All @@ -14652,9 +14658,24 @@ typedef struct
#define USB_HS_PHYC_LDO_STATUS_Pos (1U)
#define USB_HS_PHYC_LDO_STATUS_Msk (0x1U << USB_HS_PHYC_LDO_STATUS_Pos) /*!< 0x00000002 */
#define USB_HS_PHYC_LDO_STATUS USB_HS_PHYC_LDO_STATUS_Msk /*!< Monitors the status of the PHY's LDO. */
#define USB_HS_PHYC_LDO_ENABLE_Pos (2U)
#define USB_HS_PHYC_LDO_ENABLE_Msk (0x1U << USB_HS_PHYC_LDO_ENABLE_Pos) /*!< 0x00000004 */
#define USB_HS_PHYC_LDO_ENABLE USB_HS_PHYC_LDO_ENABLE_Msk /*!< Controls disable of the High Speed PHY's LDO */
#define USB_HS_PHYC_LDO_DISABLE_Pos (2U)
#define USB_HS_PHYC_LDO_DISABLE_Msk (0x1U << USB_HS_PHYC_LDO_DISABLE_Pos) /*!< 0x00000004 */
#define USB_HS_PHYC_LDO_DISABLE USB_HS_PHYC_LDO_DISABLE_Msk /*!< Controls disable of the High Speed PHY's LDO */

/* Legacy */
#define USB_HS_PHYC_PLL_PLLEN_Pos USB_HS_PHYC_PLL1_PLLEN_Pos
#define USB_HS_PHYC_PLL_PLLEN_Msk USB_HS_PHYC_PLL1_PLLEN_Msk
#define USB_HS_PHYC_PLL_PLLEN USB_HS_PHYC_PLL1_PLLEN
#define USB_HS_PHYC_PLL_PLLSEL_Pos USB_HS_PHYC_PLL1_PLLSEL_Pos
#define USB_HS_PHYC_PLL_PLLSEL_Msk USB_HS_PHYC_PLL1_PLLSEL_Msk
#define USB_HS_PHYC_PLL_PLLSEL USB_HS_PHYC_PLL1_PLLSEL
#define USB_HS_PHYC_PLL_PLLSEL_1 USB_HS_PHYC_PLL1_PLLSEL_1
#define USB_HS_PHYC_PLL_PLLSEL_2 USB_HS_PHYC_PLL1_PLLSEL_2
#define USB_HS_PHYC_PLL_PLLSEL_3 USB_HS_PHYC_PLL1_PLLSEL_3

#define USB_HS_PHYC_LDO_ENABLE_Pos USB_HS_PHYC_LDO_DISABLE_Pos
#define USB_HS_PHYC_LDO_ENABLE_Msk USB_HS_PHYC_LDO_DISABLE_Msk
#define USB_HS_PHYC_LDO_ENABLE USB_HS_PHYC_LDO_DISABLE



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47 changes: 34 additions & 13 deletions system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f733xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -14857,16 +14857,22 @@ typedef struct
#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */

/******************** Bit definition for USBPHYC_PLL register ********************/
#define USB_HS_PHYC_PLL_PLLEN_Pos (0U)
#define USB_HS_PHYC_PLL_PLLEN_Msk (0x1U << USB_HS_PHYC_PLL_PLLEN_Pos) /*!< 0x00000001 */
#define USB_HS_PHYC_PLL_PLLEN USB_HS_PHYC_PLL_PLLEN_Msk /*!< Enable PLL */
#define USB_HS_PHYC_PLL_PLLSEL_Pos (2U)
#define USB_HS_PHYC_PLL_PLLSEL_Msk (0x5U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000014 */
#define USB_HS_PHYC_PLL_PLLSEL USB_HS_PHYC_PLL_PLLSEL_Msk /*!< Controls PHY frequency operation selection */
#define USB_HS_PHYC_PLL_PLLSEL_1 (0x0U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000002 */
#define USB_HS_PHYC_PLL_PLLSEL_2 (0x1U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000004 */
#define USB_HS_PHYC_PLL_PLLSEL_3 (0x2U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000008 */
/******************** Bit definition for USBPHYC_PLL1 register ********************/
#define USB_HS_PHYC_PLL1_PLLEN_Pos (0U)
#define USB_HS_PHYC_PLL1_PLLEN_Msk (0x1U << USB_HS_PHYC_PLL1_PLLEN_Pos) /*!< 0x00000001 */
#define USB_HS_PHYC_PLL1_PLLEN USB_HS_PHYC_PLL1_PLLEN_Msk /*!< Enable PLL */
#define USB_HS_PHYC_PLL1_PLLSEL_Pos (1U)
#define USB_HS_PHYC_PLL1_PLLSEL_Msk (0x7U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x0000000E */
#define USB_HS_PHYC_PLL1_PLLSEL USB_HS_PHYC_PLL1_PLLSEL_Msk /*!< Controls PHY frequency operation selection */
#define USB_HS_PHYC_PLL1_PLLSEL_1 (0x1U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000002 */
#define USB_HS_PHYC_PLL1_PLLSEL_2 (0x2U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000004 */
#define USB_HS_PHYC_PLL1_PLLSEL_3 (0x4U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000008 */

#define USB_HS_PHYC_PLL1_PLLSEL_12MHZ 0x00000000U /*!< PHY PLL1 input clock frequency 12 MHz */
#define USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ USB_HS_PHYC_PLL1_PLLSEL_1 /*!< PHY PLL1 input clock frequency 12.5 MHz */
#define USB_HS_PHYC_PLL1_PLLSEL_16MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_1 | USB_HS_PHYC_PLL1_PLLSEL_2) /*!< PHY PLL1 input clock frequency 16 MHz */
#define USB_HS_PHYC_PLL1_PLLSEL_24MHZ USB_HS_PHYC_PLL1_PLLSEL_3 /*!< PHY PLL1 input clock frequency 24 MHz */
#define USB_HS_PHYC_PLL1_PLLSEL_25MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_2 | USB_HS_PHYC_PLL1_PLLSEL_3) /*!< PHY PLL1 input clock frequency 25 MHz */

/******************** Bit definition for USBPHYC_LDO register ********************/
#define USB_HS_PHYC_LDO_USED_Pos (0U)
Expand All @@ -14875,9 +14881,24 @@ typedef struct
#define USB_HS_PHYC_LDO_STATUS_Pos (1U)
#define USB_HS_PHYC_LDO_STATUS_Msk (0x1U << USB_HS_PHYC_LDO_STATUS_Pos) /*!< 0x00000002 */
#define USB_HS_PHYC_LDO_STATUS USB_HS_PHYC_LDO_STATUS_Msk /*!< Monitors the status of the PHY's LDO. */
#define USB_HS_PHYC_LDO_ENABLE_Pos (2U)
#define USB_HS_PHYC_LDO_ENABLE_Msk (0x1U << USB_HS_PHYC_LDO_ENABLE_Pos) /*!< 0x00000004 */
#define USB_HS_PHYC_LDO_ENABLE USB_HS_PHYC_LDO_ENABLE_Msk /*!< Controls disable of the High Speed PHY's LDO */
#define USB_HS_PHYC_LDO_DISABLE_Pos (2U)
#define USB_HS_PHYC_LDO_DISABLE_Msk (0x1U << USB_HS_PHYC_LDO_DISABLE_Pos) /*!< 0x00000004 */
#define USB_HS_PHYC_LDO_DISABLE USB_HS_PHYC_LDO_DISABLE_Msk /*!< Controls disable of the High Speed PHY's LDO */

/* Legacy */
#define USB_HS_PHYC_PLL_PLLEN_Pos USB_HS_PHYC_PLL1_PLLEN_Pos
#define USB_HS_PHYC_PLL_PLLEN_Msk USB_HS_PHYC_PLL1_PLLEN_Msk
#define USB_HS_PHYC_PLL_PLLEN USB_HS_PHYC_PLL1_PLLEN
#define USB_HS_PHYC_PLL_PLLSEL_Pos USB_HS_PHYC_PLL1_PLLSEL_Pos
#define USB_HS_PHYC_PLL_PLLSEL_Msk USB_HS_PHYC_PLL1_PLLSEL_Msk
#define USB_HS_PHYC_PLL_PLLSEL USB_HS_PHYC_PLL1_PLLSEL
#define USB_HS_PHYC_PLL_PLLSEL_1 USB_HS_PHYC_PLL1_PLLSEL_1
#define USB_HS_PHYC_PLL_PLLSEL_2 USB_HS_PHYC_PLL1_PLLSEL_2
#define USB_HS_PHYC_PLL_PLLSEL_3 USB_HS_PHYC_PLL1_PLLSEL_3

#define USB_HS_PHYC_LDO_ENABLE_Pos USB_HS_PHYC_LDO_DISABLE_Pos
#define USB_HS_PHYC_LDO_ENABLE_Msk USB_HS_PHYC_LDO_DISABLE_Msk
#define USB_HS_PHYC_LDO_ENABLE USB_HS_PHYC_LDO_DISABLE



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4 changes: 2 additions & 2 deletions system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -109,11 +109,11 @@
#endif /* USE_HAL_DRIVER */

/**
* @brief CMSIS Device version number V1.2.1
* @brief CMSIS Device version number V1.2.2
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
Expand Down
7 changes: 5 additions & 2 deletions system/Drivers/CMSIS/Device/ST/STM32F7xx/Release_Notes.html
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28 changes: 25 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h
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Expand Up @@ -423,10 +423,12 @@ typedef struct
typedef struct
{
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
} RI_TypeDef;

/**
Expand Down Expand Up @@ -5584,6 +5586,26 @@ typedef struct
#define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */
#define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */

/******************** Bit definition for RI_HYSCR3 register ********************/
#define RI_HYSCR3_PE_Pos (0U)
#define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */
#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */
#define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */
#define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */
#define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */
#define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */
#define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */
#define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */
#define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */
#define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */
#define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */
#define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */
#define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */
#define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */
#define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */
#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */

/******************************************************************************/
/* */
Expand Down
28 changes: 25 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h
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Original file line number Diff line number Diff line change
Expand Up @@ -423,10 +423,12 @@ typedef struct
typedef struct
{
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
} RI_TypeDef;

/**
Expand Down Expand Up @@ -5732,6 +5734,26 @@ typedef struct
#define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */
#define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */

/******************** Bit definition for RI_HYSCR3 register ********************/
#define RI_HYSCR3_PE_Pos (0U)
#define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */
#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */
#define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */
#define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */
#define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */
#define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */
#define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */
#define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */
#define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */
#define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */
#define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */
#define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */
#define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */
#define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */
#define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */
#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */

/******************************************************************************/
/* */
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