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system(H7) update STM32H7xx HAL Drivers to v1.11.0 and CMSIS Drivers to v1.10.2 #1686

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Merged
merged 3 commits into from
Apr 12, 2022
Merged

system(H7) update STM32H7xx HAL Drivers to v1.11.0 and CMSIS Drivers to v1.10.2 #1686

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0a87b6c
system(H7) update STM32H7xx HAL Drivers to v1.11.0
ABOSTM Apr 8, 2022
d15bde4
system(H7): update STM32H7xx CMSIS Drivers to v1.10.2
ABOSTM Apr 8, 2022
afee23e
core(H7): update wrapped files
ABOSTM Apr 8, 2022
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2 changes: 2 additions & 0 deletions libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c
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Expand Up @@ -6,6 +6,8 @@
#include "stm32g0xx_hal_smbus_ex.c"
#elif STM32G4xx
#include "stm32g4xx_hal_smbus_ex.c"
#elif STM32H7xx
#include "stm32h7xx_hal_smbus_ex.c"
#elif STM32L0xx
#include "stm32l0xx_hal_smbus_ex.c"
#elif STM32L4xx
Expand Down
11 changes: 8 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h
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Expand Up @@ -2757,6 +2757,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down Expand Up @@ -20348,9 +20351,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
Expand All @@ -20364,6 +20364,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */

/* Legacy define */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */

/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
Expand Down
11 changes: 8 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h
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Expand Up @@ -2758,6 +2758,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down Expand Up @@ -20360,9 +20363,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
Expand All @@ -20376,6 +20376,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */

/* Legacy define */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */

/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
Expand Down
11 changes: 8 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h
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Expand Up @@ -2892,6 +2892,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down Expand Up @@ -20835,9 +20838,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
Expand All @@ -20851,6 +20851,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */

/* Legacy define */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */

/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
Expand Down
11 changes: 8 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h
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Expand Up @@ -2893,6 +2893,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down Expand Up @@ -20847,9 +20850,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
Expand All @@ -20863,6 +20863,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */

/* Legacy define */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */

/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
Expand Down
11 changes: 8 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h
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Expand Up @@ -2892,6 +2892,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down Expand Up @@ -20835,9 +20838,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
Expand All @@ -20851,6 +20851,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */

/* Legacy define */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */

/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
Expand Down
11 changes: 8 additions & 3 deletions system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h735xx.h
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Expand Up @@ -2893,6 +2893,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down Expand Up @@ -20847,9 +20850,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
Expand All @@ -20863,6 +20863,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */

/* Legacy define */
#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */

/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
Expand Down
3 changes: 3 additions & 0 deletions system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h
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Expand Up @@ -2675,6 +2675,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down
5 changes: 4 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
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Expand Up @@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
Expand Down Expand Up @@ -2770,6 +2770,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down
5 changes: 4 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xg.h
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Expand Up @@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
Expand Down Expand Up @@ -2864,6 +2864,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down
3 changes: 3 additions & 0 deletions system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h
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Expand Up @@ -2864,6 +2864,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down
5 changes: 4 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xg.h
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Expand Up @@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
Expand Down Expand Up @@ -2947,6 +2947,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down
3 changes: 3 additions & 0 deletions system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h
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Expand Up @@ -2947,6 +2947,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
Expand Down
5 changes: 4 additions & 1 deletion system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h
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Expand Up @@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* Copyright (c) 2018 STMicroelectronics.
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
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#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
#define ADC_ISR_LDORDY_Pos (12U)
#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */

/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
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