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Merged
merged 5 commits into from
Aug 5, 2020
Merged

Update STM32G4 HAL and CMSIS drivers #1137

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1d55525
[G4] Update STM32G4xx HAL Drivers to v1.2.0
fpistm Aug 4, 2020
5e32e9d
[G4] Update STM32G4xx CMSIS Drivers to v1.2.0
fpistm Aug 4, 2020
bef3857
[G4] Update wrapped files
fpistm Aug 4, 2020
6dd4526
[G4] Fix LL FMC build issue introduce in HAL version v1.1.1
fpistm Apr 4, 2020
9cc22c7
[G4] Set default HSE_VALUE to 24MHz
fpistm Aug 5, 2020
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4 changes: 4 additions & 0 deletions cores/arduino/stm32/stm32_def_build.h
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Original file line number Diff line number Diff line change
Expand Up @@ -198,6 +198,10 @@
#define CMSIS_STARTUP_FILE "startup_stm32g483xx.s"
#elif defined(STM32G484xx)
#define CMSIS_STARTUP_FILE "startup_stm32g484xx.s"
#elif defined(STM32G491xx)
#define CMSIS_STARTUP_FILE "startup_stm32g491xx.s"
#elif defined(STM32G4A1xx)
#define CMSIS_STARTUP_FILE "startup_stm32g4a1xx.s"
#elif defined(STM32GBK1CB)
#define CMSIS_STARTUP_FILE "startup_stm32gbk1cb.s"
#elif defined(STM32H742xx)
Expand Down
20 changes: 5 additions & 15 deletions system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1438,10 +1438,6 @@ typedef struct
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */

#define ADC_CFGR2_LFTRIG_Pos (29U)
#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */

/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
Expand Down Expand Up @@ -2228,11 +2224,11 @@ typedef struct

#define COMP_CSR_BRGEN_Pos (22U)
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */

#define COMP_CSR_SCALEN_Pos (23U)
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */

#define COMP_CSR_VALUE_Pos (30U)
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
Expand Down Expand Up @@ -2303,7 +2299,6 @@ typedef struct
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */


/******************************************************************************/
/* */
/* CRC calculation unit */
Expand Down Expand Up @@ -2452,9 +2447,9 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */

/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
Expand Down Expand Up @@ -2658,7 +2653,6 @@ typedef struct
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */


#define DAC_SR_DAC2RDY_Pos (27U)
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
Expand Down Expand Up @@ -2874,7 +2868,6 @@ typedef struct
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk

/******************** Bit definition for DBGMCU_APB1FZR2 register **********/

/******************** Bit definition for DBGMCU_APB2FZ register ************/
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
Expand Down Expand Up @@ -9932,6 +9925,7 @@ typedef struct
#define SYSCFG_SWPR_PAGE9_Pos (9U)
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */

/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
Expand Down Expand Up @@ -12538,7 +12532,6 @@ typedef struct
*/

/******************************* ADC Instances ********************************/

#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2))

Expand Down Expand Up @@ -12618,7 +12611,6 @@ typedef struct
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3))


/******************************** PCD Instances *******************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

Expand Down Expand Up @@ -12945,7 +12937,6 @@ typedef struct
((INSTANCE) == TIM15))

/****************** TIM Instances : supporting OCxREF clear *******************/

#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
Expand Down Expand Up @@ -13000,7 +12991,6 @@ typedef struct
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))


/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
Expand Down
21 changes: 5 additions & 16 deletions system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g441xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1472,10 +1472,6 @@ typedef struct
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */

#define ADC_CFGR2_LFTRIG_Pos (29U)
#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */

/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
Expand Down Expand Up @@ -2407,7 +2403,6 @@ typedef struct
#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */


/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
Expand Down Expand Up @@ -2450,11 +2445,11 @@ typedef struct

#define COMP_CSR_BRGEN_Pos (22U)
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */

#define COMP_CSR_SCALEN_Pos (23U)
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */

#define COMP_CSR_VALUE_Pos (30U)
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
Expand Down Expand Up @@ -2525,7 +2520,6 @@ typedef struct
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */


/******************************************************************************/
/* */
/* CRC calculation unit */
Expand Down Expand Up @@ -2674,9 +2668,9 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */

/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
Expand Down Expand Up @@ -2880,7 +2874,6 @@ typedef struct
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */


#define DAC_SR_DAC2RDY_Pos (27U)
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
Expand Down Expand Up @@ -3096,7 +3089,6 @@ typedef struct
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk

/******************** Bit definition for DBGMCU_APB1FZR2 register **********/

/******************** Bit definition for DBGMCU_APB2FZ register ************/
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
Expand Down Expand Up @@ -10163,6 +10155,7 @@ typedef struct
#define SYSCFG_SWPR_PAGE9_Pos (9U)
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */

/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
Expand Down Expand Up @@ -12769,7 +12762,6 @@ typedef struct
*/

/******************************* ADC Instances ********************************/

#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2))

Expand Down Expand Up @@ -12851,7 +12843,6 @@ typedef struct
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3))


/******************************** PCD Instances *******************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

Expand Down Expand Up @@ -13178,7 +13169,6 @@ typedef struct
((INSTANCE) == TIM15))

/****************** TIM Instances : supporting OCxREF clear *******************/

#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
Expand Down Expand Up @@ -13233,7 +13223,6 @@ typedef struct
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))


/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
Expand Down
19 changes: 5 additions & 14 deletions system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g471xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1502,10 +1502,6 @@ typedef struct
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */

#define ADC_CFGR2_LFTRIG_Pos (29U)
#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */

/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
Expand Down Expand Up @@ -2292,11 +2288,11 @@ typedef struct

#define COMP_CSR_BRGEN_Pos (22U)
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */

#define COMP_CSR_SCALEN_Pos (23U)
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */

#define COMP_CSR_VALUE_Pos (30U)
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
Expand Down Expand Up @@ -2367,7 +2363,6 @@ typedef struct
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */


/******************************************************************************/
/* */
/* CRC calculation unit */
Expand Down Expand Up @@ -2516,9 +2511,9 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */

/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
Expand Down Expand Up @@ -2722,7 +2717,6 @@ typedef struct
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */


#define DAC_SR_DAC2RDY_Pos (27U)
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
Expand Down Expand Up @@ -10440,6 +10434,7 @@ typedef struct
#define SYSCFG_SWPR_PAGE31_Pos (31U)
#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/

/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
Expand Down Expand Up @@ -13056,7 +13051,6 @@ typedef struct
((INSTANCE) == ADC345_COMMON) )



/******************************** FDCAN Instances ******************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
((INSTANCE) == FDCAN2))
Expand Down Expand Up @@ -13134,7 +13128,6 @@ typedef struct
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3))


/******************************** PCD Instances *******************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

Expand Down Expand Up @@ -13500,7 +13493,6 @@ typedef struct
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))


/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
Expand Down Expand Up @@ -13549,7 +13541,6 @@ typedef struct
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))


/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
Expand Down
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