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system(H5): update STM32H5xx CMSIS Drivers to v1.2.0
Included in STM32CubeH5 FW v1.2.0 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 713a020 commit 6dc7119

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Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h523xx.h

+660
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Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h533xx.h

+664
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Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h562xx.h

+124-95
Original file line numberDiff line numberDiff line change
@@ -13,17 +13,24 @@
1313
* - Setup Interrupt Target
1414
*
1515
******************************************************************************
16-
* @attention
16+
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
17+
* Copyright (c) 2023 STMicroelectronics. All rights reserved.
1718
*
18-
* Copyright (c) 2023 STMicroelectronics.
19-
* All rights reserved.
19+
* SPDX-License-Identifier: Apache-2.0
2020
*
21-
* This software is licensed under terms that can be found in the LICENSE file
22-
* in the root directory of this software component.
23-
* If no LICENSE file comes with this software, it is provided AS-IS.
21+
* Licensed under the Apache License, Version 2.0 (the License); you may
22+
* not use this file except in compliance with the License.
23+
* You may obtain a copy of the License at
2424
*
25+
* www.apache.org/licenses/LICENSE-2.0
26+
*
27+
* Unless required by applicable law or agreed to in writing, software
28+
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
29+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
30+
* See the License for the specific language governing permissions and
31+
* limitations under the License.
2532
******************************************************************************
26-
*/
33+
*/
2734

2835
#ifndef PARTITION_STM32H562XX_H
2936
#define PARTITION_STM32H562XX_H
@@ -420,34 +427,33 @@
420427
// <o.1> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
421428
// <o.2> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
422429
// <o.3> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
423-
// <o.4> ADC1_IRQn <0=> Secure state <1=> Non-Secure state
424-
// <o.5> DAC1_IRQn <0=> Secure state <1=> Non-Secure state
425-
// <o.6> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
426-
// <o.7> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
427-
// <o.8> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
428-
// <o.9> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
429-
// <o.10> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
430-
// <o.11> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
431-
// <o.12> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
432-
// <o.13> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
433-
// <o.14> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
434-
// <o.15> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
435-
// <o.16> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
436-
// <o.17> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
437-
// <o.18> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
438-
// <o.19> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
439-
// <o.20> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
440-
// <o.21> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
441-
// <o.22> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
442-
// <o.23> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
443-
// <o.24> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
444-
// <o.25> USART1_IRQn <0=> Secure state <1=> Non-Secure state
445-
// <o.26> USART2_IRQn <0=> Secure state <1=> Non-Secure state
446-
// <o.27> USART3_IRQn <0=> Secure state <1=> Non-Secure state
447-
// <o.28> UART4_IRQn <0=> Secure state <1=> Non-Secure state
448-
// <o.29> UART5_IRQn <0=> Secure state <1=> Non-Secure state
449-
// <o.30> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
450-
// <o.31> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
430+
// <o.5> ADC1_IRQn <0=> Secure state <1=> Non-Secure state
431+
// <o.6> DAC1_IRQn <0=> Secure state <1=> Non-Secure state
432+
// <o.7> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
433+
// <o.8> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
434+
// <o.9> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
435+
// <o.10> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
436+
// <o.11> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
437+
// <o.12> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
438+
// <o.13> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
439+
// <o.14> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
440+
// <o.15> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
441+
// <o.16> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
442+
// <o.17> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
443+
// <o.18> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
444+
// <o.19> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
445+
// <o.20> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
446+
// <o.21> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
447+
// <o.22> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
448+
// <o.23> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
449+
// <o.24> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
450+
// <o.25> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
451+
// <o.26> USART1_IRQn <0=> Secure state <1=> Non-Secure state
452+
// <o.27> USART2_IRQn <0=> Secure state <1=> Non-Secure state
453+
// <o.28> USART3_IRQn <0=> Secure state <1=> Non-Secure state
454+
// <o.29> UART4_IRQn <0=> Secure state <1=> Non-Secure state
455+
// <o.30> UART5_IRQn <0=> Secure state <1=> Non-Secure state
456+
// <o.31> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
451457
*/
452458
#define NVIC_INIT_ITNS1_VAL 0x00000000
453459

@@ -462,38 +468,38 @@
462468

463469
/*
464470
// Interrupts 64..95
465-
// <o.0> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
466-
// <o.1> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
467-
// <o.2> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
468-
// <o.3> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
469-
// <o.4> ADC2_IRQn <0=> Secure state <1=> Non-Secure state
470-
// <o.5> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
471-
// <o.6> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
472-
// <o.7> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
473-
// <o.8> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
474-
// <o.9> USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state
475-
// <o.10> CRS_IRQn <0=> Secure state <1=> Non-Secure state
476-
// <o.11> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
477-
// <o.12> FMC_IRQn <0=> Secure state <1=> Non-Secure state
478-
// <o.13> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
479-
// <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
480-
// <o.15> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
481-
// <o.16> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
482-
// <o.17> SPI4_IRQn <0=> Secure state <1=> Non-Secure state
483-
// <o.18> SPI5_IRQn <0=> Secure state <1=> Non-Secure state
484-
// <o.19> SPI6_IRQn <0=> Secure state <1=> Non-Secure state
485-
// <o.20> USART6_IRQn <0=> Secure state <1=> Non-Secure state
486-
// <o.21> USART10_IRQn <0=> Secure state <1=> Non-Secure state
487-
// <o.22> USART11_IRQn <0=> Secure state <1=> Non-Secure state
488-
// <o.23> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
489-
// <o.24> SAI2_IRQn <0=> Secure state <1=> Non-Secure state
490-
// <o.25> GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
491-
// <o.26> GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
492-
// <o.27> GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
493-
// <o.28> GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
494-
// <o.29> GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
495-
// <o.30> GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
496-
// <o.31> GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
471+
// <o.0> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
472+
// <o.1> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
473+
// <o.2> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
474+
// <o.3> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
475+
// <o.4> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
476+
// <o.5> ADC2_IRQn <0=> Secure state <1=> Non-Secure state
477+
// <o.6> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
478+
// <o.7> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
479+
// <o.8> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
480+
// <o.9> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
481+
// <o.10> USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state
482+
// <o.11> CRS_IRQn <0=> Secure state <1=> Non-Secure state
483+
// <o.12> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
484+
// <o.13> FMC_IRQn <0=> Secure state <1=> Non-Secure state
485+
// <o.14> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
486+
// <o.15> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
487+
// <o.16> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
488+
// <o.17> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
489+
// <o.18> SPI4_IRQn <0=> Secure state <1=> Non-Secure state
490+
// <o.19> SPI5_IRQn <0=> Secure state <1=> Non-Secure state
491+
// <o.20> SPI6_IRQn <0=> Secure state <1=> Non-Secure state
492+
// <o.21> USART6_IRQn <0=> Secure state <1=> Non-Secure state
493+
// <o.22> USART10_IRQn <0=> Secure state <1=> Non-Secure state
494+
// <o.23> USART11_IRQn <0=> Secure state <1=> Non-Secure state
495+
// <o.24> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
496+
// <o.25> SAI2_IRQn <0=> Secure state <1=> Non-Secure state
497+
// <o.26> GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
498+
// <o.27> GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
499+
// <o.28> GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
500+
// <o.29> GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
501+
// <o.30> GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
502+
// <o.31> GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
497503
*/
498504
#define NVIC_INIT_ITNS2_VAL 0x00000000
499505

@@ -502,41 +508,60 @@
502508
*/
503509

504510
/*
505-
// <e>Initialize ITNS 3 (Interrupts 96..121)
511+
// <e>Initialize ITNS 3 (Interrupts 96..127)
506512
*/
507513
#define NVIC_INIT_ITNS3 1
508514

509515
/*
510-
// Interrupts 96..121
511-
// <o.0> GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
512-
// <o.1> UART7_IRQn <0=> Secure state <1=> Non-Secure state
513-
// <o.2> UART8_IRQn <0=> Secure state <1=> Non-Secure state
514-
// <o.3> UART9_IRQn <0=> Secure state <1=> Non-Secure state
515-
// <o.4> UART12_IRQn <0=> Secure state <1=> Non-Secure state
516-
// <o.5> FPU_IRQn <0=> Secure state <1=> Non-Secure state
517-
// <o.6> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
518-
// <o.7> DCACHE_IRQn <0=> Secure state <1=> Non-Secure state
519-
// <o.8> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
520-
// <o.9> CORDIC_IRQn <0=> Secure state <1=> Non-Secure state
521-
// <o.10> FMAC_IRQn <0=> Secure state <1=> Non-Secure state
522-
// <o.11> DTS_IRQn <0=> Secure state <1=> Non-Secure state
523-
// <o.12> RNG_IRQn <0=> Secure state <1=> Non-Secure state
524-
// <o.13> HASH_IRQn <0=> Secure state <1=> Non-Secure state
525-
// <o.14> CEC_IRQn <0=> Secure state <1=> Non-Secure state
526-
// <o.15> TIM12_IRQn <0=> Secure state <1=> Non-Secure state
527-
// <o.16> TIM13_IRQn <0=> Secure state <1=> Non-Secure state
528-
// <o.17> TIM14_IRQn <0=> Secure state <1=> Non-Secure state
529-
// <o.18> I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
530-
// <o.19> I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
531-
// <o.20> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
532-
// <o.21> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
533-
// <o.22> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
534-
// <o.23> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
535-
// <o.24> LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state
536-
// <o.25> LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state
516+
// Interrupts 96..127
517+
// <o.0> GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
518+
// <o.1> GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
519+
// <o.2> UART7_IRQn <0=> Secure state <1=> Non-Secure state
520+
// <o.3> UART8_IRQn <0=> Secure state <1=> Non-Secure state
521+
// <o.4> UART9_IRQn <0=> Secure state <1=> Non-Secure state
522+
// <o.5> UART12_IRQn <0=> Secure state <1=> Non-Secure state
523+
// <o.7> FPU_IRQn <0=> Secure state <1=> Non-Secure state
524+
// <o.8> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
525+
// <o.9> DCACHE_IRQn <0=> Secure state <1=> Non-Secure state
526+
// <o.12> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
527+
// <o.15> CORDIC_IRQn <0=> Secure state <1=> Non-Secure state
528+
// <o.16> FMAC_IRQn <0=> Secure state <1=> Non-Secure state
529+
// <o.17> DTS_IRQn <0=> Secure state <1=> Non-Secure state
530+
// <o.18> RNG_IRQn <0=> Secure state <1=> Non-Secure state
531+
// <o.21> HASH_IRQn <0=> Secure state <1=> Non-Secure state
532+
// <o.23> CEC_IRQn <0=> Secure state <1=> Non-Secure state
533+
// <o.24> TIM12_IRQn <0=> Secure state <1=> Non-Secure state
534+
// <o.25> TIM13_IRQn <0=> Secure state <1=> Non-Secure state
535+
// <o.26> TIM14_IRQn <0=> Secure state <1=> Non-Secure state
536+
// <o.27> I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
537+
// <o.28> I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
538+
// <o.29> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
539+
// <o.30> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
540+
// <o.31> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
537541
*/
538542
#define NVIC_INIT_ITNS3_VAL 0x00000000
539543

544+
/*
545+
// </e>
546+
*/
547+
548+
/*
549+
// <e>Initialize ITNS 4 (Interrupts 128..130)
550+
*/
551+
#define NVIC_INIT_ITNS4 1
552+
553+
/*
554+
// Interrupts 128..130
555+
// <o.0> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
556+
// <o.1> LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state
557+
// <o.2> LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state
558+
*/
559+
#define NVIC_INIT_ITNS4_VAL 0x00000000
560+
561+
/*
562+
// </e>
563+
*/
564+
540565
/*
541566
// </h>
542567
*/
@@ -644,6 +669,10 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
644669
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
645670
#endif
646671

672+
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
673+
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
674+
#endif
675+
647676
}
648677

649678
#endif /* PARTITION_STM32H562XX_H */

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