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Commit 6bf3069

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dojyorindojyorin
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Revert SDMMC1 clock source.
1 parent 258d8c3 commit 6bf3069

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6 files changed

+6
-6
lines changed

6 files changed

+6
-6
lines changed

Diff for: ‎variants/STM32H5xx/H562R(G-I)T/generic_clock.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ WEAK void SystemClock_Config(void)
9797
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
9898
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
9999
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
100-
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R;
100+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
101101
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
102102
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q;
103103
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;

Diff for: ‎variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -176,7 +176,7 @@ WEAK void SystemClock_Config(void)
176176
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
177177
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
178178
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
179-
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R;
179+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
180180
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
181181
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q;
182182
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;

Diff for: ‎variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ WEAK void SystemClock_Config(void)
9898
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
9999
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
100100
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
101-
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R;
101+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
102102
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
103103
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q;
104104
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;

Diff for: ‎variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ WEAK void SystemClock_Config(void)
9898
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
9999
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
100100
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
101-
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R;
101+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
102102
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
103103
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q;
104104
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;

Diff for: ‎variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ WEAK void SystemClock_Config(void)
9999
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
100100
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
101101
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
102-
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R;
102+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
103103
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
104104
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q;
105105
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;

Diff for: ‎variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -250,7 +250,7 @@ WEAK void SystemClock_Config(void)
250250
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
251251
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
252252
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
253-
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R;
253+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
254254
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
255255
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q;
256256
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;

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