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system(WBA): update STM32WBAxx CMSIS Drivers to v1.4.0
Included in STM32CubeWBA FW v1.4.1 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 8e97f16 commit 673869b

27 files changed

+320
-232
lines changed

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h

+30-27
Original file line numberDiff line numberDiff line change
@@ -253,14 +253,14 @@ typedef struct
253253
*/
254254
typedef struct
255255
{
256-
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
257-
__IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */
258-
__IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
259-
__IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
260-
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
261-
uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */
262-
__IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */
263-
__IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */
256+
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
257+
__IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */
258+
__IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
259+
__IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
260+
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
261+
uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */
262+
__IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */
263+
__IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */
264264
} DBGMCU_TypeDef;
265265

266266
/**
@@ -617,11 +617,11 @@ typedef struct
617617
*/
618618
typedef struct
619619
{
620-
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
621-
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
622-
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
620+
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
621+
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
622+
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
623623
uint32_t RESERVED;
624-
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
624+
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
625625
} RNG_TypeDef;
626626

627627
/*
@@ -693,18 +693,18 @@ typedef struct
693693
*/
694694
typedef struct
695695
{
696-
__IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
697-
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
698-
__IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
699-
__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
700-
__IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
701-
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
702-
__IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
703-
__IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
704-
__IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
705-
__IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
706-
uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
707-
__IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
696+
__IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
697+
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
698+
__IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
699+
__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
700+
__IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
701+
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
702+
__IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
703+
__IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
704+
__IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
705+
__IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
706+
uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
707+
__IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
708708
} SYSCFG_TypeDef;
709709

710710
/**
@@ -4256,7 +4256,7 @@ typedef struct
42564256
#define I2C_CR1_ADDRACLR_Pos (30U)
42574257
#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */
42584258
#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */
4259-
#define I2C_CR1_STOPFACLR_Pos (30U)
4259+
#define I2C_CR1_STOPFACLR_Pos (31U)
42604260
#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */
42614261
#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */
42624262

@@ -4942,7 +4942,6 @@ typedef struct
49424942
#define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
49434943
#define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */
49444944

4945-
49464945
/******************************************************************************/
49474946
/* */
49484947
/* Public Key Accelerator (PKA) */
@@ -6669,6 +6668,9 @@ typedef struct
66696668
#define RNG_HTCR_HTCFG_Pos (0U)
66706669
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
66716670
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
6671+
/******************** RNG Nist Compliance Values *******************/
6672+
#define RNG_CR_NIST_VALUE (0x00F02D00U)
6673+
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
66726674

66736675

66746676
/******************************************************************************/
@@ -10293,7 +10295,8 @@ typedef struct
1029310295

1029410296
/****************** TIM Instances : supporting OCxREF clear *******************/
1029510297
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
10296-
((INSTANCE) == TIM2_NS))
10298+
((INSTANCE) == TIM2_NS) || \
10299+
((INSTANCE) == TIM16_NS))
1029710300

1029810301
/********* TIM Instances : supporting bitfield OCCS in SMCR register **********/
1029910302
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h

+31-27
Original file line numberDiff line numberDiff line change
@@ -267,14 +267,14 @@ typedef struct
267267
*/
268268
typedef struct
269269
{
270-
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
271-
__IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */
272-
__IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
273-
__IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
274-
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
275-
uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */
276-
__IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */
277-
__IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */
270+
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
271+
__IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */
272+
__IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
273+
__IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
274+
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
275+
uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */
276+
__IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */
277+
__IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */
278278
} DBGMCU_TypeDef;
279279

280280
/**
@@ -710,11 +710,11 @@ typedef struct
710710
*/
711711
typedef struct
712712
{
713-
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
714-
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
715-
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
713+
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
714+
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
715+
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
716716
uint32_t RESERVED;
717-
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
717+
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
718718
} RNG_TypeDef;
719719

720720
/*
@@ -787,18 +787,18 @@ typedef struct
787787
*/
788788
typedef struct
789789
{
790-
__IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
791-
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
792-
__IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
793-
__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
794-
__IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
795-
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
796-
__IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
797-
__IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
798-
__IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
799-
__IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
800-
uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
801-
__IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
790+
__IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
791+
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
792+
__IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
793+
__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
794+
__IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
795+
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
796+
__IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
797+
__IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
798+
__IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
799+
__IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
800+
uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
801+
__IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
802802
} SYSCFG_TypeDef;
803803

804804
/**
@@ -7856,7 +7856,7 @@ typedef struct
78567856
#define I2C_CR1_ADDRACLR_Pos (30U)
78577857
#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */
78587858
#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */
7859-
#define I2C_CR1_STOPFACLR_Pos (30U)
7859+
#define I2C_CR1_STOPFACLR_Pos (31U)
78607860
#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */
78617861
#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */
78627862

@@ -8542,7 +8542,6 @@ typedef struct
85428542
#define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
85438543
#define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */
85448544

8545-
85468545
/******************************************************************************/
85478546
/* */
85488547
/* Public Key Accelerator (PKA) */
@@ -10570,6 +10569,9 @@ typedef struct
1057010569
#define RNG_HTCR_HTCFG_Pos (0U)
1057110570
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
1057210571
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
10572+
/******************** RNG Nist Compliance Values *******************/
10573+
#define RNG_CR_NIST_VALUE (0x00F02D00U)
10574+
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
1057310575

1057410576

1057510577
/******************************************************************************/
@@ -14527,7 +14529,9 @@ typedef struct
1452714529
/****************** TIM Instances : supporting OCxREF clear *******************/
1452814530
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
1452914531
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
14530-
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
14532+
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \
14533+
((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
14534+
((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
1453114535

1453214536
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
1453314537
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \

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