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system(WBA) update STM32WBAxx HAL Drivers to v1.4.0
Included in STM32CubeWBA FW v1.4.1 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 6a03b54 commit 8e97f16

39 files changed

+1259
-448
lines changed

Diff for: ‎system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+23-2
Original file line numberDiff line numberDiff line change
@@ -806,6 +806,21 @@ extern "C" {
806806
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
807807
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
808808
#endif /* STM32U5 */
809+
810+
#if defined(STM32WBA)
811+
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
812+
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
813+
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
814+
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
815+
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
816+
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
817+
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
818+
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
819+
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
820+
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
821+
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
822+
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
823+
#endif /* STM32WBA */
809824
/**
810825
* @}
811826
*/
@@ -1817,7 +1832,7 @@ extern "C" {
18171832
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
18181833
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
18191834

1820-
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
1835+
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
18211836
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
18221837
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
18231838

@@ -2731,6 +2746,12 @@ extern "C" {
27312746
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
27322747
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
27332748
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
2749+
#if defined(STM32C0)
2750+
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
2751+
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
2752+
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
2753+
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
2754+
#endif /* STM32C0 */
27342755
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
27352756
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
27362757
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -3910,7 +3931,7 @@ extern "C" {
39103931
*/
39113932
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
39123933
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3913-
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
3934+
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
39143935
#else
39153936
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39163937
#endif

Diff for: ‎system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h

+177-5
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ extern HAL_TickFreqTypeDef uwTickFreq;
7979
* @brief STM32WBAxx HAL Driver version number
8080
*/
8181
#define __STM32WBAxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
82-
#define __STM32WBAxx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
82+
#define __STM32WBAxx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
8383
#define __STM32WBAxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
8484
#define __STM32WBAxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
8585
#define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\
@@ -119,6 +119,38 @@ extern HAL_TickFreqTypeDef uwTickFreq;
119119
* @}
120120
*/
121121

122+
/** @defgroup SYSCFG_Compensation_Cell_Selection Compensation Cell Selection
123+
* @{
124+
*/
125+
#define SYSCFG_IO_CELL SYSCFG_CCCSR_EN1 /*!< Compensation cell for the VDD I/O power rail */
126+
#ifdef SYSCFG_CCCSR_EN2
127+
#define SYSCFG_IO2_CELL SYSCFG_CCCSR_EN2 /*!< Compensation cell for the VDDIO2 I/O power rail */
128+
#endif /* SYSCFG_CCCSR_EN2 */
129+
/**
130+
* @}
131+
*/
132+
133+
/** @defgroup SYSCFG_Compensation_Cell_Ready_Selection Compensation Cell Ready Selection
134+
* @{
135+
*/
136+
#define SYSCFG_IO_CELL_READY SYSCFG_CCCSR_RDY1 /*!< Ready flag of compensation cell for the VDD I/O power rail */
137+
#ifdef SYSCFG_CCCSR_EN2
138+
#define SYSCFG_IO2_CELL_READY SYSCFG_CCCSR_RDY2 /*!< Ready flag of compensation cell for the VDDIO2 I/O power rail */
139+
#endif /* SYSCFG_CCCSR_EN2 */
140+
/**
141+
* @}
142+
*/
143+
144+
/** @defgroup SYSCFG_IO_Compensation_Code_Config IO Compensation Code config
145+
* @{
146+
*/
147+
#define SYSCFG_IO_CELL_CODE 0UL /*!< Code from the cell */
148+
#define SYSCFG_IO_REGISTER_CODE 1UL /*!< Code from the values in the cell code register */
149+
/**
150+
* @}
151+
*/
152+
153+
122154
/** @defgroup SYSCFG_Flags_Definition Flags
123155
* @{
124156
*/
@@ -188,6 +220,83 @@ extern HAL_TickFreqTypeDef uwTickFreq;
188220
* @}
189221
*/
190222

223+
#ifdef SYSCFG_OTGHSPHYCR_EN
224+
/** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection
225+
* @{
226+
*/
227+
228+
/** @brief OTG HS PHY reference clock frequency selection
229+
*/
230+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */
231+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */
232+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */
233+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */
234+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */
235+
#define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */
236+
/**
237+
* @}
238+
*/
239+
240+
/** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down
241+
* @{
242+
*/
243+
244+
/** @brief OTG HS PHY Power Down config
245+
*/
246+
#define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */
247+
#define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */
248+
/**
249+
* @}
250+
*/
251+
252+
/** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable
253+
* @{
254+
*/
255+
#define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */
256+
#define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */
257+
/**
258+
* @}
259+
*/
260+
261+
/** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current
262+
* @{
263+
*/
264+
265+
/** @brief High-speed (HS) transmitter preemphasis current control
266+
*/
267+
#define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */
268+
#define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */
269+
#define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */
270+
#define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */
271+
/**
272+
* @}
273+
*/
274+
275+
/** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold
276+
* @{
277+
*/
278+
279+
/** @brief Squelch threshold adjustment
280+
*/
281+
#define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */
282+
#define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */
283+
/**
284+
* @}
285+
*/
286+
287+
/** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold
288+
* @{
289+
*/
290+
291+
/** @brief Disconnect threshold adjustment
292+
*/
293+
#define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */
294+
#define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */
295+
/**
296+
* @}
297+
*/
298+
#endif /* SYSCFG_OTGHSPHYCR_EN */
299+
191300
/**
192301
* @}
193302
*/
@@ -391,11 +500,31 @@ extern HAL_TickFreqTypeDef uwTickFreq;
391500
#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_ALL) != 0x00U) && \
392501
(((__INTERRUPT__) & ~SYSCFG_IT_FPU_ALL) == 0x00U))
393502

503+
#ifdef SYSCFG_CCCSR_EN2
504+
#define IS_SYSCFG_COMPENSATION_CELL(__CELL__) (((__CELL__) == SYSCFG_IO_CELL) || \
505+
((__CELL__) == SYSCFG_IO2_CELL))
506+
507+
#define IS_SYSCFG_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SYSCFG_IO_CELL_READY) || \
508+
((__CELL__) == SYSCFG_IO2_CELL_READY))
509+
#else
510+
#define IS_SYSCFG_COMPENSATION_CELL(__CELL__) (((__CELL__) == SYSCFG_IO_CELL))
511+
512+
#define IS_SYSCFG_COMPENSATION_CELL_READY(__CELL__) (((__CELL__) == SYSCFG_IO_CELL_READY))
513+
#endif /* SYSCFG_CCCSR_EN2 */
514+
515+
#define IS_SYSCFG_COMPENSATION_CELL_CODE(__VALUE__) (((__VALUE__) == SYSCFG_IO_CELL_CODE) || \
516+
((__VALUE__) == SYSCFG_IO_REGISTER_CODE))
517+
518+
#define IS_SYSCFG_COMPENSATION_CELL_PMOS_VALUE(__VALUE__) (((__VALUE__) < 16U))
519+
520+
#define IS_SYSCFG_COMPENSATION_CELL_NMOS_VALUE(__VALUE__) (((__VALUE__) < 16U))
521+
394522
#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \
395523
((__CONFIG__) == SYSCFG_BREAK_PVD) || \
396524
((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \
397525
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
398526

527+
399528
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_ALL) != 0x00U) && \
400529
(((__PIN__) & ~SYSCFG_FASTMODEPLUS_ALL) == 0x00U))
401530

@@ -418,6 +547,31 @@ extern HAL_TickFreqTypeDef uwTickFreq;
418547
#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_LOCK_ALL) != 0x00U) && \
419548
(((__ITEM__) & ~SYSCFG_LOCK_ALL) == 0x00U))
420549

550+
#ifdef SYSCFG_OTGHSPHYCR_EN
551+
#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \
552+
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \
553+
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \
554+
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \
555+
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \
556+
((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6))
557+
558+
#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \
559+
((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON))
560+
561+
#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \
562+
((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE))
563+
564+
#define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \
565+
((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT))
566+
567+
#define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \
568+
((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT))
569+
570+
#define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \
571+
((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \
572+
((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \
573+
((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X))
574+
#endif /* SYSCFG_OTGHSPHYCR_EN */
421575

422576
/**
423577
* @}
@@ -487,10 +641,28 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void);
487641
*/
488642

489643
/* SYSCFG Control functions ****************************************************/
490-
void HAL_SYSCFG_SRAM2Erase(void);
491644
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
492645
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
493-
646+
void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void);
647+
void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void);
648+
649+
650+
#ifdef SYSCFG_OTGHSPHYCR_EN
651+
void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClockSelection);
652+
void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig);
653+
void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig);
654+
void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold);
655+
void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold);
656+
void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent);
657+
#endif /* SYSCFG_OTGHSPHYCR_EN */
658+
659+
void HAL_SYSCFG_EnableCompensationCell(uint32_t Selection);
660+
void HAL_SYSCFG_DisableCompensationCell(uint32_t Selection);
661+
uint32_t HAL_SYSCFG_GetCompensationCellReadyStatus(uint32_t Selection);
662+
void HAL_SYSCFG_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue,
663+
uint32_t PmosValue);
664+
HAL_StatusTypeDef HAL_SYSCFG_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue,
665+
uint32_t *pPmosValue);
494666
/**
495667
* @}
496668
*/
@@ -500,7 +672,7 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
500672
*/
501673

502674
/* SYSCFG Lock functions ********************************************/
503-
void HAL_SYSCFG_Lock(uint32_t Item);
675+
void HAL_SYSCFG_Lock(uint32_t Item);
504676
HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem);
505677

506678
/**
@@ -514,7 +686,7 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem);
514686
#if defined (SYSCFG_SECCFGR_SYSCFGSEC)
515687
/* SYSCFG Attributes functions ********************************************/
516688
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
517-
void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes);
689+
void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes);
518690
#endif /* __ARM_FEATURE_CMSE */
519691
HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
520692
#endif /* SYSCFG_SECCFGR_SYSCFGSEC */

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