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add the llvm.x86.sse42.crc32.32.32 intrinsic #1488

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Merged
merged 2 commits into from
May 11, 2024
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add the llvm.x86.sse42.crc32.32.32 intrinsic #1488

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add the `llvm.x86.sse42.crc32.32.32` intrinsic
folkertdev May 11, 2024
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folkertdev May 11, 2024
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26 changes: 26 additions & 0 deletions src/intrinsics/llvm_x86.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -832,6 +832,32 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
}
}

"llvm.x86.sse42.crc32.32.32" => {
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#ig_expand=939,1419,1419&text=_mm_crc32_u32
intrinsic_args!(fx, args => (crc, v); intrinsic);

let crc = crc.load_scalar(fx);
let v = v.load_scalar(fx);

codegen_inline_asm_inner(
fx,
&[InlineAsmTemplatePiece::String("crc32 eax, edx".to_string())],
&[
CInlineAsmOperand::InOut {
reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::ax)),
_late: true,
in_value: crc,
out_place: Some(ret),
},
CInlineAsmOperand::In {
reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::dx)),
value: v,
},
Comment on lines +846 to +855
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is there any particular reason to choose particular register names here? this seemed to be the ordering used in some of the other examples.

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There is no particular reason for the choice of registers.

],
InlineAsmOptions::NOSTACK | InlineAsmOptions::PURE | InlineAsmOptions::NOMEM,
);
}

"llvm.x86.sse42.pcmpestri128" => {
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpestri&ig_expand=939
intrinsic_args!(fx, args => (a, la, b, lb, _imm8); intrinsic);
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