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2 parents 5d5e0b0 + 8ab795e commit 6c91efdCopy full SHA for 6c91efd
compiler/rustc_codegen_llvm/src/context.rs
@@ -145,8 +145,13 @@ pub unsafe fn create_module<'ll>(
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let llvm_version = llvm_util::get_version();
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if llvm_version < (16, 0, 0) {
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if sess.target.arch == "s390x" {
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+ // LLVM 16 data layout changed to always set 64-bit vector alignment,
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+ // which is conditional in earlier LLVM versions.
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+ // https://reviews.llvm.org/D131158 for the discussion.
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target_data_layout = target_data_layout.replace("-v128:64", "");
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} else if sess.target.arch == "riscv64" {
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+ // LLVM 16 introduced this change so as to produce more efficient code.
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+ // See https://reviews.llvm.org/D116735 for the discussion.
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target_data_layout = target_data_layout.replace("-n32:64-", "-n64-");
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}
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