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CodeGen: Convert some TII hooks to use Register
1 parent 178050c commit 30ebafa

22 files changed

+159
-159
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -235,8 +235,8 @@ class TargetInstrInfo : public MCInstrInfo {
235235
/// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
236236
/// expected the pre-extension value is available as a subreg of the result
237237
/// register. This also returns the sub-register index in SubIdx.
238-
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
239-
unsigned &DstReg, unsigned &SubIdx) const {
238+
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
239+
Register &DstReg, unsigned &SubIdx) const {
240240
return false;
241241
}
242242

@@ -368,7 +368,7 @@ class TargetInstrInfo : public MCInstrInfo {
368368
/// DestReg:SubIdx. Any existing subreg index is preserved or composed with
369369
/// SubIdx.
370370
virtual void reMaterialize(MachineBasicBlock &MBB,
371-
MachineBasicBlock::iterator MI, unsigned DestReg,
371+
MachineBasicBlock::iterator MI, Register DestReg,
372372
unsigned SubIdx, const MachineInstr &Orig,
373373
const TargetRegisterInfo &TRI) const;
374374

@@ -448,10 +448,10 @@ class TargetInstrInfo : public MCInstrInfo {
448448
/// A pair composed of a register and a sub-register index.
449449
/// Used to give some type checking when modeling Reg:SubReg.
450450
struct RegSubRegPair {
451-
unsigned Reg;
451+
Register Reg;
452452
unsigned SubReg;
453453

454-
RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
454+
RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
455455
: Reg(Reg), SubReg(SubReg) {}
456456

457457
bool operator==(const RegSubRegPair& P) const {
@@ -468,7 +468,7 @@ class TargetInstrInfo : public MCInstrInfo {
468468
struct RegSubRegPairAndIdx : RegSubRegPair {
469469
unsigned SubIdx;
470470

471-
RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
471+
RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0,
472472
unsigned SubIdx = 0)
473473
: RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
474474
};
@@ -845,8 +845,8 @@ class TargetInstrInfo : public MCInstrInfo {
845845
/// @param TrueCycles Latency from TrueReg to select output.
846846
/// @param FalseCycles Latency from FalseReg to select output.
847847
virtual bool canInsertSelect(const MachineBasicBlock &MBB,
848-
ArrayRef<MachineOperand> Cond, unsigned DstReg,
849-
unsigned TrueReg, unsigned FalseReg,
848+
ArrayRef<MachineOperand> Cond, Register DstReg,
849+
Register TrueReg, Register FalseReg,
850850
int &CondCycles, int &TrueCycles,
851851
int &FalseCycles) const {
852852
return false;
@@ -869,8 +869,8 @@ class TargetInstrInfo : public MCInstrInfo {
869869
/// @param FalseReg Virtual register to copy when Cons is false.
870870
virtual void insertSelect(MachineBasicBlock &MBB,
871871
MachineBasicBlock::iterator I, const DebugLoc &DL,
872-
unsigned DstReg, ArrayRef<MachineOperand> Cond,
873-
unsigned TrueReg, unsigned FalseReg) const {
872+
Register DstReg, ArrayRef<MachineOperand> Cond,
873+
Register TrueReg, Register FalseReg) const {
874874
llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
875875
}
876876

@@ -1416,16 +1416,16 @@ class TargetInstrInfo : public MCInstrInfo {
14161416
/// in SrcReg and SrcReg2 if having two register operands, and the value it
14171417
/// compares against in CmpValue. Return true if the comparison instruction
14181418
/// can be analyzed.
1419-
virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1420-
unsigned &SrcReg2, int &Mask, int &Value) const {
1419+
virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1420+
Register &SrcReg2, int &Mask, int &Value) const {
14211421
return false;
14221422
}
14231423

14241424
/// See if the comparison instruction can be converted
14251425
/// into something more efficient. E.g., on ARM most instructions can set the
14261426
/// flags register, obviating the need for a separate CMP.
1427-
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1428-
unsigned SrcReg2, int Mask, int Value,
1427+
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1428+
Register SrcReg2, int Mask, int Value,
14291429
const MachineRegisterInfo *MRI) const {
14301430
return false;
14311431
}
@@ -1452,7 +1452,7 @@ class TargetInstrInfo : public MCInstrInfo {
14521452
/// block. The caller may assume that it will not be erased by this
14531453
/// function otherwise.
14541454
virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1455-
unsigned Reg, MachineRegisterInfo *MRI) const {
1455+
Register Reg, MachineRegisterInfo *MRI) const {
14561456
return false;
14571457
}
14581458

‎llvm/lib/CodeGen/PeepholeOptimizer.cpp

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -457,12 +457,12 @@ INITIALIZE_PASS_END(PeepholeOptimizer, DEBUG_TYPE,
457457
bool PeepholeOptimizer::
458458
optimizeExtInstr(MachineInstr &MI, MachineBasicBlock &MBB,
459459
SmallPtrSetImpl<MachineInstr*> &LocalMIs) {
460-
unsigned SrcReg, DstReg, SubIdx;
460+
Register SrcReg, DstReg;
461+
unsigned SubIdx;
461462
if (!TII->isCoalescableExtInstr(MI, SrcReg, DstReg, SubIdx))
462463
return false;
463464

464-
if (Register::isPhysicalRegister(DstReg) ||
465-
Register::isPhysicalRegister(SrcReg))
465+
if (DstReg.isPhysical() || SrcReg.isPhysical())
466466
return false;
467467

468468
if (MRI->hasOneNonDBGUse(SrcReg))
@@ -607,11 +607,10 @@ optimizeExtInstr(MachineInstr &MI, MachineBasicBlock &MBB,
607607
bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr &MI) {
608608
// If this instruction is a comparison against zero and isn't comparing a
609609
// physical register, we can try to optimize it.
610-
unsigned SrcReg, SrcReg2;
610+
Register SrcReg, SrcReg2;
611611
int CmpMask, CmpValue;
612612
if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
613-
Register::isPhysicalRegister(SrcReg) ||
614-
(SrcReg2 != 0 && Register::isPhysicalRegister(SrcReg2)))
613+
SrcReg.isPhysical() || SrcReg2.isPhysical())
615614
return false;
616615

617616
// Attempt to optimize the comparison instruction.
@@ -663,8 +662,8 @@ bool PeepholeOptimizer::findNextSource(RegSubRegPair RegSubReg,
663662
// So far we do not have any motivating example for doing that.
664663
// Thus, instead of maintaining untested code, we will revisit that if
665664
// that changes at some point.
666-
unsigned Reg = RegSubReg.Reg;
667-
if (Register::isPhysicalRegister(Reg))
665+
Register Reg = RegSubReg.Reg;
666+
if (Reg.isPhysical())
668667
return false;
669668
const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
670669

‎llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -486,8 +486,8 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
486486
for (SDNode *User : Node->uses()) {
487487
if (User->getOpcode() == ISD::CopyToReg &&
488488
User->getOperand(2).getNode() == Node) {
489-
unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
490-
if (Register::isVirtualRegister(DestReg)) {
489+
Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
490+
if (DestReg.isVirtual()) {
491491
VRBase = DestReg;
492492
break;
493493
}
@@ -502,7 +502,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
502502
const TargetRegisterClass *TRC =
503503
TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
504504

505-
unsigned Reg;
505+
Register Reg;
506506
MachineInstr *DefMI;
507507
RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
508508
if (R && Register::isPhysicalRegister(R->getReg())) {
@@ -513,7 +513,8 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
513513
DefMI = MRI->getVRegDef(Reg);
514514
}
515515

516-
unsigned SrcReg, DstReg, DefSubIdx;
516+
Register SrcReg, DstReg;
517+
unsigned DefSubIdx;
517518
if (DefMI &&
518519
TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
519520
SubIdx == DefSubIdx &&
@@ -531,7 +532,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
531532
// Reg may not support a SubIdx sub-register, and we may need to
532533
// constrain its register class or issue a COPY to a compatible register
533534
// class.
534-
if (Register::isVirtualRegister(Reg))
535+
if (Reg.isVirtual())
535536
Reg = ConstrainForSubReg(Reg, SubIdx,
536537
Node->getOperand(0).getSimpleValueType(),
537538
Node->isDivergent(), Node->getDebugLoc());
@@ -543,7 +544,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
543544
MachineInstrBuilder CopyMI =
544545
BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
545546
TII->get(TargetOpcode::COPY), VRBase);
546-
if (Register::isVirtualRegister(Reg))
547+
if (Reg.isVirtual())
547548
CopyMI.addReg(Reg, 0, SubIdx);
548549
else
549550
CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));

‎llvm/lib/CodeGen/TargetInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -408,7 +408,7 @@ bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
408408

409409
void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
410410
MachineBasicBlock::iterator I,
411-
unsigned DestReg, unsigned SubIdx,
411+
Register DestReg, unsigned SubIdx,
412412
const MachineInstr &Orig,
413413
const TargetRegisterInfo &TRI) const {
414414
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -510,8 +510,8 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
510510

511511
bool AArch64InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
512512
ArrayRef<MachineOperand> Cond,
513-
unsigned DstReg, unsigned TrueReg,
514-
unsigned FalseReg, int &CondCycles,
513+
Register DstReg, Register TrueReg,
514+
Register FalseReg, int &CondCycles,
515515
int &TrueCycles,
516516
int &FalseCycles) const {
517517
// Check register classes.
@@ -559,9 +559,9 @@ bool AArch64InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
559559

560560
void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
561561
MachineBasicBlock::iterator I,
562-
const DebugLoc &DL, unsigned DstReg,
562+
const DebugLoc &DL, Register DstReg,
563563
ArrayRef<MachineOperand> Cond,
564-
unsigned TrueReg, unsigned FalseReg) const {
564+
Register TrueReg, Register FalseReg) const {
565565
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
566566

567567
// Parse the condition code, see parseCondBranch() above.
@@ -931,7 +931,7 @@ bool AArch64InstrInfo::isSEHInstruction(const MachineInstr &MI) {
931931
}
932932

933933
bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
934-
unsigned &SrcReg, unsigned &DstReg,
934+
Register &SrcReg, Register &DstReg,
935935
unsigned &SubIdx) const {
936936
switch (MI.getOpcode()) {
937937
default:
@@ -1011,8 +1011,8 @@ bool AArch64InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
10111011
/// analyzeCompare - For a comparison instruction, return the source registers
10121012
/// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
10131013
/// Return true if the comparison instruction can be analyzed.
1014-
bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1015-
unsigned &SrcReg2, int &CmpMask,
1014+
bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1015+
Register &SrcReg2, int &CmpMask,
10161016
int &CmpValue) const {
10171017
// The first operand can be a frame index where we'd normally expect a
10181018
// register.
@@ -1207,7 +1207,7 @@ static bool areCFlagsAccessedBetweenInstrs(
12071207
/// instruction.
12081208
/// Only comparison with zero is supported.
12091209
bool AArch64InstrInfo::optimizeCompareInstr(
1210-
MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
1210+
MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int CmpMask,
12111211
int CmpValue, const MachineRegisterInfo *MRI) const {
12121212
assert(CmpInstr.getParent());
12131213
assert(MRI);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
5252

5353
bool isAsCheapAsAMove(const MachineInstr &MI) const override;
5454

55-
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
56-
unsigned &DstReg, unsigned &SubIdx) const override;
55+
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
56+
Register &DstReg, unsigned &SubIdx) const override;
5757

5858
bool
5959
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
@@ -197,12 +197,12 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
197197
bool
198198
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
199199
bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
200-
unsigned, unsigned, unsigned, int &, int &,
200+
Register, Register, Register, int &, int &,
201201
int &) const override;
202202
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
203-
const DebugLoc &DL, unsigned DstReg,
204-
ArrayRef<MachineOperand> Cond, unsigned TrueReg,
205-
unsigned FalseReg) const override;
203+
const DebugLoc &DL, Register DstReg,
204+
ArrayRef<MachineOperand> Cond, Register TrueReg,
205+
Register FalseReg) const override;
206206
void getNoop(MCInst &NopInst) const override;
207207

208208
bool isSchedulingBoundary(const MachineInstr &MI,
@@ -212,13 +212,13 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
212212
/// analyzeCompare - For a comparison instruction, return the source registers
213213
/// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
214214
/// Return true if the comparison instruction can be analyzed.
215-
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
216-
unsigned &SrcReg2, int &CmpMask,
215+
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
216+
Register &SrcReg2, int &CmpMask,
217217
int &CmpValue) const override;
218218
/// optimizeCompareInstr - Convert the instruction supplying the argument to
219219
/// the comparison into one that sets the zero bit in the flags register.
220-
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
221-
unsigned SrcReg2, int CmpMask, int CmpValue,
220+
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
221+
Register SrcReg2, int CmpMask, int CmpValue,
222222
const MachineRegisterInfo *MRI) const override;
223223
bool optimizeCondBranch(MachineInstr &MI) const override;
224224

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -812,10 +812,10 @@ SIInstrInfo::getPreferredSelectRegClass(unsigned Size) const {
812812

813813
void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
814814
MachineBasicBlock::iterator I,
815-
const DebugLoc &DL, unsigned DstReg,
815+
const DebugLoc &DL, Register DstReg,
816816
ArrayRef<MachineOperand> Cond,
817-
unsigned TrueReg,
818-
unsigned FalseReg) const {
817+
Register TrueReg,
818+
Register FalseReg) const {
819819
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
820820
MachineFunction *MF = MBB.getParent();
821821
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
@@ -2205,8 +2205,8 @@ bool SIInstrInfo::reverseBranchCondition(
22052205

22062206
bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
22072207
ArrayRef<MachineOperand> Cond,
2208-
unsigned DstReg, unsigned TrueReg,
2209-
unsigned FalseReg, int &CondCycles,
2208+
Register DstReg, Register TrueReg,
2209+
Register FalseReg, int &CondCycles,
22102210
int &TrueCycles, int &FalseCycles) const {
22112211
switch (Cond[0].getImm()) {
22122212
case VCCNZ:
@@ -2245,8 +2245,8 @@ bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
22452245

22462246
void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,
22472247
MachineBasicBlock::iterator I, const DebugLoc &DL,
2248-
unsigned DstReg, ArrayRef<MachineOperand> Cond,
2249-
unsigned TrueReg, unsigned FalseReg) const {
2248+
Register DstReg, ArrayRef<MachineOperand> Cond,
2249+
Register TrueReg, Register FalseReg) const {
22502250
BranchPredicate Pred = static_cast<BranchPredicate>(Cond[0].getImm());
22512251
if (Pred == VCCZ || Pred == SCC_FALSE) {
22522252
Pred = static_cast<BranchPredicate>(-Pred);
@@ -2393,7 +2393,7 @@ static void removeModOperands(MachineInstr &MI) {
23932393
}
23942394

23952395
bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
2396-
unsigned Reg, MachineRegisterInfo *MRI) const {
2396+
Register Reg, MachineRegisterInfo *MRI) const {
23972397
if (!MRI->hasOneNonDBGUse(Reg))
23982398
return false;
23992399

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -297,19 +297,19 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
297297
SmallVectorImpl<MachineOperand> &Cond) const override;
298298

299299
bool canInsertSelect(const MachineBasicBlock &MBB,
300-
ArrayRef<MachineOperand> Cond, unsigned DstReg,
301-
unsigned TrueReg, unsigned FalseReg, int &CondCycles,
300+
ArrayRef<MachineOperand> Cond, Register DstReg,
301+
Register TrueReg, Register FalseReg, int &CondCycles,
302302
int &TrueCycles, int &FalseCycles) const override;
303303

304304
void insertSelect(MachineBasicBlock &MBB,
305305
MachineBasicBlock::iterator I, const DebugLoc &DL,
306-
unsigned DstReg, ArrayRef<MachineOperand> Cond,
307-
unsigned TrueReg, unsigned FalseReg) const override;
306+
Register DstReg, ArrayRef<MachineOperand> Cond,
307+
Register TrueReg, Register FalseReg) const override;
308308

309309
void insertVectorSelect(MachineBasicBlock &MBB,
310310
MachineBasicBlock::iterator I, const DebugLoc &DL,
311-
unsigned DstReg, ArrayRef<MachineOperand> Cond,
312-
unsigned TrueReg, unsigned FalseReg) const;
311+
Register DstReg, ArrayRef<MachineOperand> Cond,
312+
Register TrueReg, Register FalseReg) const;
313313

314314
unsigned getAddressSpaceForPseudoSourceKind(
315315
unsigned Kind) const override;
@@ -320,7 +320,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
320320

321321
bool isFoldableCopy(const MachineInstr &MI) const;
322322

323-
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
323+
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
324324
MachineRegisterInfo *MRI) const final;
325325

326326
unsigned getMachineCSELookAheadLimit() const override { return 500; }

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