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arsenmarsenm
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AMDGPU: Use Register in more places
1 parent e8dcb6d commit 178050c

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6 files changed

+77
-81
lines changed

6 files changed

+77
-81
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2099,7 +2099,7 @@ void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
20992099

21002100
bool UseSCCBr = isCBranchSCC(N) && isUniformBr(N);
21012101
unsigned BrOp = UseSCCBr ? AMDGPU::S_CBRANCH_SCC1 : AMDGPU::S_CBRANCH_VCCNZ;
2102-
unsigned CondReg = UseSCCBr ? (unsigned)AMDGPU::SCC : TRI->getVCC();
2102+
Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC();
21032103
SDLoc SL(N);
21042104

21052105
if (!UseSCCBr) {

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10862,8 +10862,8 @@ bool SITargetLowering::isSDNodeSourceOfDivergence(const SDNode * N,
1086210862
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
1086310863
const MachineRegisterInfo &MRI = MF->getRegInfo();
1086410864
const SIRegisterInfo &TRI = ST.getInstrInfo()->getRegisterInfo();
10865-
unsigned Reg = R->getReg();
10866-
if (Register::isPhysicalRegister(Reg))
10865+
Register Reg = R->getReg();
10866+
if (Reg.isPhysical())
1086710867
return !TRI.isSGPRReg(MRI, Reg);
1086810868

1086910869
if (MRI.isLiveIn(Reg)) {

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -654,7 +654,7 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
654654
// Registers in the sequence are allocated contiguously so we can just
655655
// use register number to pick one of three round-robin temps.
656656
unsigned RegNo = DestReg % 3;
657-
unsigned Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
657+
Register Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
658658
if (!Tmp)
659659
report_fatal_error("Cannot scavenge VGPR to copy to AGPR");
660660
RS.setRegUsed(Tmp);
@@ -938,10 +938,10 @@ void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
938938
}
939939
}
940940

941-
unsigned SIInstrInfo::insertEQ(MachineBasicBlock *MBB,
941+
Register SIInstrInfo::insertEQ(MachineBasicBlock *MBB,
942942
MachineBasicBlock::iterator I,
943943
const DebugLoc &DL,
944-
unsigned SrcReg, int Value) const {
944+
Register SrcReg, int Value) const {
945945
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
946946
Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
947947
BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg)
@@ -951,10 +951,10 @@ unsigned SIInstrInfo::insertEQ(MachineBasicBlock *MBB,
951951
return Reg;
952952
}
953953

954-
unsigned SIInstrInfo::insertNE(MachineBasicBlock *MBB,
954+
Register SIInstrInfo::insertNE(MachineBasicBlock *MBB,
955955
MachineBasicBlock::iterator I,
956956
const DebugLoc &DL,
957-
unsigned SrcReg, int Value) const {
957+
Register SrcReg, int Value) const {
958958
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
959959
Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
960960
BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg)
@@ -1274,7 +1274,7 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
12741274
// FIXME: Maybe this should not include a memoperand because it will be
12751275
// lowered to non-memory instructions.
12761276
const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
1277-
if (Register::isVirtualRegister(DestReg) && SpillSize == 4) {
1277+
if (DestReg.isVirtual() && SpillSize == 4) {
12781278
MachineRegisterInfo &MRI = MF->getRegInfo();
12791279
MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0RegClass);
12801280
}
@@ -1315,7 +1315,7 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(
13151315
unsigned WorkGroupSize = MFI->getMaxFlatWorkGroupSize();
13161316
unsigned WavefrontSize = ST.getWavefrontSize();
13171317

1318-
unsigned TIDReg = MFI->getTIDReg();
1318+
Register TIDReg = MFI->getTIDReg();
13191319
if (!MFI->hasCalculatedTID()) {
13201320
MachineBasicBlock &Entry = MBB.getParent()->front();
13211321
MachineBasicBlock::iterator Insert = Entry.front();
@@ -1343,8 +1343,8 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(
13431343

13441344
RS->enterBasicBlock(Entry);
13451345
// FIXME: Can we scavenge an SReg_64 and access the subregs?
1346-
unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
1347-
unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
1346+
Register STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
1347+
Register STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
13481348
BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
13491349
.addReg(InputPtrReg)
13501350
.addImm(SI::KernelInputOffsets::NGROUPS_Z);
@@ -2319,7 +2319,7 @@ void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,
23192319

23202320
I = MIB->getIterator();
23212321

2322-
SmallVector<unsigned, 8> Regs;
2322+
SmallVector<Register, 8> Regs;
23232323
for (int Idx = 0; Idx != NElts; ++Idx) {
23242324
Register DstElt = MRI.createVirtualRegister(EltRC);
23252325
Regs.push_back(DstElt);
@@ -3215,7 +3215,7 @@ bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
32153215
}
32163216
}
32173217

3218-
static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
3218+
static Register findImplicitSGPRRead(const MachineInstr &MI) {
32193219
for (const MachineOperand &MO : MI.implicit_operands()) {
32203220
// We only care about reads.
32213221
if (MO.isDef())
@@ -3523,8 +3523,8 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
35233523
if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1)
35243524
++ConstantBusCount;
35253525

3526-
SmallVector<unsigned, 2> SGPRsUsed;
3527-
unsigned SGPRUsed = findImplicitSGPRRead(MI);
3526+
SmallVector<Register, 2> SGPRsUsed;
3527+
Register SGPRUsed = findImplicitSGPRRead(MI);
35283528
if (SGPRUsed != AMDGPU::NoRegister) {
35293529
++ConstantBusCount;
35303530
SGPRsUsed.push_back(SGPRUsed);
@@ -4316,7 +4316,7 @@ void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
43164316
}
43174317
}
43184318

4319-
unsigned SIInstrInfo::readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
4319+
Register SIInstrInfo::readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,
43204320
MachineRegisterInfo &MRI) const {
43214321
const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
43224322
const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC);
@@ -5722,7 +5722,7 @@ void SIInstrInfo::splitScalar64BitBFE(SetVectorType &Worklist,
57225722
}
57235723

57245724
void SIInstrInfo::addUsersToMoveToVALUWorklist(
5725-
unsigned DstReg,
5725+
Register DstReg,
57265726
MachineRegisterInfo &MRI,
57275727
SetVectorType &Worklist) const {
57285728
for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
@@ -5888,7 +5888,7 @@ const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
58885888
}
58895889

58905890
// Find the one SGPR operand we are allowed to use.
5891-
unsigned SIInstrInfo::findUsedSGPR(const MachineInstr &MI,
5891+
Register SIInstrInfo::findUsedSGPR(const MachineInstr &MI,
58925892
int OpIndices[3]) const {
58935893
const MCInstrDesc &Desc = MI.getDesc();
58945894

@@ -5901,11 +5901,11 @@ unsigned SIInstrInfo::findUsedSGPR(const MachineInstr &MI,
59015901
//
59025902
// If the operand's class is an SGPR, we can never move it.
59035903

5904-
unsigned SGPRReg = findImplicitSGPRRead(MI);
5904+
Register SGPRReg = findImplicitSGPRRead(MI);
59055905
if (SGPRReg != AMDGPU::NoRegister)
59065906
return SGPRReg;
59075907

5908-
unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
5908+
Register UsedSGPRs[3] = { AMDGPU::NoRegister };
59095909
const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
59105910

59115911
for (unsigned i = 0; i < 3; ++i) {
@@ -6296,7 +6296,7 @@ MachineInstrBuilder
62966296
SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,
62976297
MachineBasicBlock::iterator I,
62986298
const DebugLoc &DL,
6299-
unsigned DestReg) const {
6299+
Register DestReg) const {
63006300
if (ST.hasAddNoCarry())
63016301
return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e64), DestReg);
63026302

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
119119
MachineRegisterInfo &MRI,
120120
MachineInstr &Inst) const;
121121

122-
void addUsersToMoveToVALUWorklist(unsigned Reg, MachineRegisterInfo &MRI,
122+
void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
123123
SetVectorType &Worklist) const;
124124

125125
void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
@@ -132,7 +132,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
132132
bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
133133
const MachineInstr &MIb) const;
134134

135-
unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
135+
Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
136136

137137
protected:
138138
bool swapSourceModifiers(MachineInstr &MI,
@@ -211,13 +211,13 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
211211
const TargetRegisterClass *getPreferredSelectRegClass(
212212
unsigned Size) const;
213213

214-
unsigned insertNE(MachineBasicBlock *MBB,
214+
Register insertNE(MachineBasicBlock *MBB,
215215
MachineBasicBlock::iterator I, const DebugLoc &DL,
216-
unsigned SrcReg, int Value) const;
216+
Register SrcReg, int Value) const;
217217

218-
unsigned insertEQ(MachineBasicBlock *MBB,
218+
Register insertEQ(MachineBasicBlock *MBB,
219219
MachineBasicBlock::iterator I, const DebugLoc &DL,
220-
unsigned SrcReg, int Value) const;
220+
Register SrcReg, int Value) const;
221221

222222
void storeRegToStackSlot(MachineBasicBlock &MBB,
223223
MachineBasicBlock::iterator MI, Register SrcReg,
@@ -877,7 +877,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
877877
/// be used when it is know that the value in SrcReg is same across all
878878
/// threads in the wave.
879879
/// \returns The SGPR register that \p SrcReg was copied to.
880-
unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
880+
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,
881881
MachineRegisterInfo &MRI) const;
882882

883883
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
@@ -998,7 +998,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
998998
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
999999
MachineBasicBlock::iterator I,
10001000
const DebugLoc &DL,
1001-
unsigned DestReg) const;
1001+
Register DestReg) const;
10021002

10031003
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
10041004
MachineBasicBlock::iterator I,

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