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Add SysTick flags #116

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Merged
merged 5 commits into from
Oct 3, 2018
Merged

Add SysTick flags #116

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19d3534
Added Pending SV (Service Call) and SysTick flags
qwerty19106 Sep 24, 2018
454bb4e
Fix duplicate PendSV.
qwerty19106 Sep 24, 2018
d9ad9d4
Fix function names and remove exclusive access
qwerty19106 Oct 1, 2018
fac7e85
Remove blank line
qwerty19106 Oct 1, 2018
2cb6f4b
Autoformat scb.rs by rustfmt
qwerty19106 Oct 1, 2018
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28 changes: 28 additions & 0 deletions src/peripheral/scb.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -619,6 +619,9 @@ impl SCB {
const SCB_ICSR_PENDSVSET: u32 = 1 << 28;
const SCB_ICSR_PENDSVCLR: u32 = 1 << 27;

const SCB_ICSR_PENDSTSET: u32 = 1 << 26;
const SCB_ICSR_PENDSTCLR: u32 = 1 << 25;

impl SCB {
/// Set the PENDSVSET bit in the ICSR register which will pend the PendSV interrupt
pub fn set_pendsv() {
Expand All @@ -640,4 +643,29 @@ impl SCB {
(*Self::ptr()).icsr.write(SCB_ICSR_PENDSVCLR);
}
}

/// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
#[inline]
pub fn set_systick(&mut self) {
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I'm not sure about calling this set_systick when just above we have set_pendsv. Really this one should be set_pendst or we need to rename both (causing a major version change). Same applies to is_systick_pending and clear_systick_pending. I'd prefer just using pendst here.

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Yes, set_pendst looks better.

unsafe {
(*Self::ptr()).icsr.write(SCB_ICSR_PENDSTSET);
}
}

/// Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending
#[inline]
pub fn is_systick_pending() -> bool {
unsafe {
(*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET
}
}


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Minor nit: One blank line too many.

/// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
#[inline]
pub fn clear_systick_pending(&mut self) {
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Does this operation require exclusive access to SCB (&mut self)? With clear_pendsv() it wasn't required because setting just the PENDSTCLR bit doesn't affect any other bits in the register, so you can't have data races.

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@qwerty19106 qwerty19106 Oct 1, 2018 •
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Yes, exclusive access to SCB is not required. I think that clear_systick_pending needs to change analogiously.

unsafe {
(*Self::ptr()).icsr.write(SCB_ICSR_PENDSTCLR);
}
}
}