Merge branch 'master' of https://github.com/rogerclarkmelbourne/Arduino_STM32

Author: stevstrong

STM32F1/cores/maple/libmaple/i2c.c

@@ -409,6 +409,24 @@ int32 i2c_master_xfer(i2c_dev *dev,
         // with state changes in the IRQ handlers:
         dev->state = I2C_STATE_ERROR;
         if (rc == I2C_ERROR_TIMEOUT) dev->error_flags |= I2C_SR1_TIMEOUT;
+        if (!(dev->config_flags & I2C_SLAVE_MODE) &&
+            (dev->error_flags & (I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_TIMEOUT))
+            ) {    // In Master Mode, we need to abort the transmission with a STOP
+                   // for NACK, Bus Error, or Timeout
+            uint32 cr1;
+            while ((cr1 = dev->regs->CR1) & (I2C_CR1_START |
+                                             I2C_CR1_STOP  |
+                                             I2C_CR1_PEC)) {
+                ;   // Must wait for pending start/stop/pec before setting stop to avoid
+                    //  accidental restart condition. See ST RM0008 Note in 26.6.1 (I2C_CR1)
+            }
+            dev->regs->CR1 |= I2C_CR1_STOP;
+            while ((cr1 = dev->regs->CR1) & (I2C_CR1_START |
+                                             I2C_CR1_STOP  |
+                                             I2C_CR1_PEC)) {
+                ;
+            }
+        }
     } else {
         dev->state = I2C_STATE_IDLE;
     }
@@ -782,14 +800,10 @@ void _i2c_irq_error_handler(i2c_dev *dev) {
             dev->state = I2C_STATE_IDLE;
             return;
         }
-    } else {
-        // Master should send a STOP on NACK:
-        if (sr1 & I2C_SR1_AF) {
-            dev->regs->CR1 |= I2C_CR1_STOP;
-        }
     }
 
-    /* Catch any other strange errors while in slave mode.
+    /* Catch any other strange errors while in slave mode and
+     * all errors in master mode (which are handled by outer loop).
      * I have seen BERR caused by an over fast master device
      * as well as several overflows and arbitration failures.
      * We are going to reset SR flags and carry on at this point which

STM32F1/libraries/STM32ADC/examples/SingleChannelContinuousConversion/SingleChannelContinuousConversion.ino

@@ -5,7 +5,7 @@
 */
 #include <STM32ADC.h>
 
-ADC myAdc(ADC1);
+STM32ADC myAdc(ADC1);
 
 void setup() {
   Serial.begin(19200);

STM32F1/libraries/Wire/Wire.cpp

@@ -44,13 +44,15 @@ uint8 TwoWire::process(uint8 stop) {
         if (sel_hard->error_flags & I2C_SR1_AF) { /* NACK */
             res = (sel_hard->error_flags & I2C_SR1_ADDR ? ENACKADDR : 
                                                           ENACKTRNS);
-        } else if (sel_hard->error_flags & I2C_SR1_OVR) { /* Over/Underrun */
-            res = EDATA;
-        } else { /* Bus or Arbitration error */
-            res = EOTHER;
+        } else {
+            if (sel_hard->error_flags & I2C_SR1_OVR) { /* Over/Underrun */
+                res = EDATA;
+            } else { /* Bus or Arbitration error */
+                res = EOTHER;
+            }
+            i2c_disable(sel_hard);
+            i2c_master_enable(sel_hard, dev_flags, frequency);
         }
-        i2c_disable(sel_hard);
-        i2c_master_enable(sel_hard, dev_flags, frequency);
     }
     return res;
 }

STM32F4/cores/maple/libmaple/adc.c

@@ -74,6 +74,7 @@ const adc_dev adc3 = {
     .handler_p = &adc3Handlers
 };
 
+
 adc_common_reg_map* const ADC_COMMON = ADC_COMMON_BASE;
 
 /**
@@ -148,6 +149,12 @@ void adc_awd_enable_irq(const adc_dev * dev)
     nvic_irq_enable(NVIC_ADC_1_2_3);
 }
 
+void adc_ovr_enable_irq(const adc_dev* dev)
+{
+    dev->regs->CR1 |= ADC_CR1_OVRIE;
+    nvic_irq_enable(NVIC_ADC_1_2_3);
+}
+
 /*
     attach interrupt functionality for ADC
     use ADC_EOC, ADC_JEOC, ADC_AWD
@@ -160,7 +167,12 @@ void adc_attach_interrupt(const adc_dev *dev,
     if (irq_id<ADC_LAST_IRQ_ID)
     {
         (*(dev->handler_p))[irq_id] = handler;
-        adc_enable_irq(dev);
+        if(irq_id == ADC_EOC)
+        	adc_enable_irq(dev);
+        else if (irq_id == ADC_AWD)
+        	adc_awd_enable_irq(dev);
+        else if (irq_id == ADC_OVR)
+        	adc_ovr_enable_irq(dev);
     }
 }
 
@@ -183,6 +195,16 @@ void adc_foreach(void (*fn)(const adc_dev*))
     fn(ADC3);
 }
 
+/*
+ *  @param pre, setup the ADC prescaler to one of PCLK /2, /4, /6, /8
+ *         the templates per adc_prescaler enum
+ */
+void adc_set_prescaler(adc_prescaler pre) {
+
+	ADC_COMMON->CCR &= ~ ADC_CCR_ADCPRE;
+	ADC_COMMON->CCR |= ((pre & 3U) << ADC_CCR_ADCPRE_SHIFT);
+}
+
 /**
  * @brief Set the given sampling times for all channels.
  *        Don't call this during conversion!
@@ -303,6 +325,15 @@ void adc_irq_handler(const adc_dev * dev)
             handler();
         }
     }
+    //ADC overrun interrupt
+    if (dev->regs->SR & ADC_SR_OVR) {
+        dev->regs->SR = ~ADC_SR_OVR;
+        voidFuncPtr handler = (*(dev->handler_p))[ADC_OVR];
+        if (handler) {
+            handler();
+        }
+    }
+
 }
 
 void __irq_adc()

STM32F4/cores/maple/libmaple/adc.h

@@ -72,6 +72,7 @@ typedef enum {
     ADC_EOC,     // End Of Conversion interrupt.
     ADC_AWD ,    // Analog WatchDog interrupt
     ADC_JEOC,    // Injected End Of Conversion interrupt.
+	ADC_OVR,	 // overrun interrupt
 	ADC_LAST_IRQ_ID
 } adc_irq_id;
 
@@ -92,9 +93,10 @@ typedef struct adc_dev
 extern const adc_dev adc1;
 extern const adc_dev adc2;
 extern const adc_dev adc3;
-#define ADC1 (&adc1)
-#define ADC2 (&adc2)
-#define ADC3 (&adc3)
+
+#define ADC1 ((adc_dev*) &adc1)
+#define ADC2 ((adc_dev*) &adc2)
+#define ADC3 ((adc_dev*) &adc3)
 
 typedef struct adc_common_reg_map {
 	__IO uint32 CSR;            ///< Common status register
@@ -303,6 +305,7 @@ extern adc_common_reg_map* const ADC_COMMON;
 #define ADC_CCR_DELAY_SHIFT             8
 #define ADC_CCR_MULTI_SHIFT             0
 
+
 #define ADC_CCR_TSVREFE                 (0x1 << ADC_CCR_TSVREFE_BIT)
 #define ADC_CCR_VBATE                   (0x1 << ADC_CCR_VBATE_BIT)
 #define ADC_CCR_ADCPRE                  (0x3 << ADC_CCR_ADCPRE_SHIFT)
@@ -311,6 +314,20 @@ extern adc_common_reg_map* const ADC_COMMON;
 #define ADC_CCR_DELAY                   (0xF << ADC_CCR_DELAY_SHIFT)
 #define ADC_CCR_MULTI                   (0x1F << ADC_CCR_MULTI_SHIFT)
 
+/**
+ * @brief STM32F1/F4 ADC prescalers, as divisors of PCLK2.
+ */
+typedef enum adc_prescaler {
+    /** PCLK2 divided by 2 */
+    ADC_PRE_PCLK2_DIV_2 = 0,
+    /** PCLK2 divided by 4 */
+    ADC_PRE_PCLK2_DIV_4 = 1,
+    /** PCLK2 divided by 6 */
+    ADC_PRE_PCLK2_DIV_6 = 2,
+    /** PCLK2 divided by 8 */
+    ADC_PRE_PCLK2_DIV_8 = 3,
+} adc_prescaler;
+
 /* Common regular data register */
 
 #define ADC_CDR_DATA2                   (0xFFFF << 16)
@@ -384,6 +401,7 @@ typedef enum {
     ADC_SMPR_480,              /**< 480 ADC cycles */
 } adc_smp_rate;
 
+void adc_set_prescaler(adc_prescaler pre);
 void adc_set_sampling_time(const adc_dev *dev, adc_smp_rate smp_rate);
 void adc_set_exttrig(const adc_dev *dev, adc_ext_trigger trigger);
 void adc_set_jextrig(const adc_dev *dev, adc_ext_trigger trigger);
@@ -392,6 +410,7 @@ void adc_set_jextsel(const adc_dev *dev, adc_jextsel_event event);
 void adc_foreach(void (*fn)(const adc_dev*));
 void adc_enable_irq(const adc_dev* dev);
 void adc_disable_irq(const adc_dev* dev);
+void adc_ovr_enable_irq(const adc_dev* dev);
 void adc_attach_interrupt(const adc_dev *dev, adc_irq_id irq_id, voidFuncPtr handler);
 void adc_set_reg_sequence(const adc_dev * dev, uint8 * channels, uint8 len);
 void adc_enable_tsvref(void);
@@ -478,6 +497,11 @@ static inline void adc_awd_enable(const adc_dev * dev)
 	dev->regs->CR1 |= ADC_CR1_AWDEN;
 }
 
+static inline void adc_awd_disable(const adc_dev * dev)
+{
+	dev->regs->CR1 &= ~ADC_CR1_AWDEN;
+}
+
 static inline void adc_set_scan_mode(const adc_dev * dev)
 {
 	dev->regs->CR1 |= ADC_CR1_SCAN;
@@ -534,6 +558,7 @@ static inline void adc_start_convert(const adc_dev * dev)
 }
 
 
+
 #ifdef __cplusplus
 } // extern "C"
 #endif