@@ -409,6 +409,24 @@ int32 i2c_master_xfer(i2c_dev *dev,
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// with state changes in the IRQ handlers:
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dev -> state = I2C_STATE_ERROR ;
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if (rc == I2C_ERROR_TIMEOUT ) dev -> error_flags |= I2C_SR1_TIMEOUT ;
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+ if (!(dev -> config_flags & I2C_SLAVE_MODE ) &&
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+ (dev -> error_flags & (I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_TIMEOUT ))
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+ ) { // In Master Mode, we need to abort the transmission with a STOP
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+ // for NACK, Bus Error, or Timeout
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+ uint32 cr1 ;
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+ while ((cr1 = dev -> regs -> CR1 ) & (I2C_CR1_START |
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+ I2C_CR1_STOP |
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+ I2C_CR1_PEC )) {
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+ ; // Must wait for pending start/stop/pec before setting stop to avoid
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+ // accidental restart condition. See ST RM0008 Note in 26.6.1 (I2C_CR1)
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+ }
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+ dev -> regs -> CR1 |= I2C_CR1_STOP ;
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+ while ((cr1 = dev -> regs -> CR1 ) & (I2C_CR1_START |
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+ I2C_CR1_STOP |
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+ I2C_CR1_PEC )) {
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+ ;
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+ }
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+ }
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} else {
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dev -> state = I2C_STATE_IDLE ;
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}
@@ -782,14 +800,10 @@ void _i2c_irq_error_handler(i2c_dev *dev) {
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dev -> state = I2C_STATE_IDLE ;
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return ;
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}
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- } else {
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- // Master should send a STOP on NACK:
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- if (sr1 & I2C_SR1_AF ) {
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- dev -> regs -> CR1 |= I2C_CR1_STOP ;
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- }
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}
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- /* Catch any other strange errors while in slave mode.
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+ /* Catch any other strange errors while in slave mode and
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+ * all errors in master mode (which are handled by outer loop).
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* I have seen BERR caused by an over fast master device
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* as well as several overflows and arbitration failures.
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* We are going to reset SR flags and carry on at this point which
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