@@ -255,6 +255,36 @@ multiclass RVVIntBinBuiltinSet {
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defm "" : RVVUnsignedBinBuiltinSet;
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}
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+ multiclass RVVSignedShiftBuiltinSet {
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+ defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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+ [["vv", "v", "vvUv"],
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+ ["vx", "v", "vvz"]]>;
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+ }
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+
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+ multiclass RVVUnsignedShiftBuiltinSet {
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+ defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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+ [["vv", "Uv", "UvUvUv"],
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+ ["vx", "Uv", "UvUvz"]]>;
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+ }
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+
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+ multiclass RVVShiftBuiltinSet {
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+ defm "" : RVVSignedShiftBuiltinSet;
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+ defm "" : RVVUnsignedShiftBuiltinSet;
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+ }
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+
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+ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
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+ multiclass RVVSignedNShiftBuiltinSet {
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+ defm "" : RVVOutOp0Op1BuiltinSet<NAME, "csil",
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+ [["wv", "v", "vwUv"],
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+ ["wx", "v", "vwz"]]>;
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+ }
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+ multiclass RVVUnsignedNShiftBuiltinSet {
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+ defm "" : RVVOutOp0Op1BuiltinSet<NAME, "csil",
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+ [["wv", "Uv", "UvUwUv"],
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+ ["wx", "Uv", "UvUwz"]]>;
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+ }
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+ }
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+
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multiclass RVVIntTerBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "v", "vvvv"],
@@ -518,27 +548,13 @@ defm vxor : RVVIntBinBuiltinSet;
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defm vor : RVVIntBinBuiltinSet;
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// 12.6. Vector Single-Width Bit Shift Instructions
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- defm vsll : RVVOutOp1BuiltinSet<"vsll", "csil",
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- [["vv", "v", "vvUv"],
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- ["vx", "v", "vvz"],
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- ["vv", "Uv", "UvUvUv"],
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- ["vx", "Uv", "UvUvz"]]>;
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- defm vsrl : RVVOutOp1BuiltinSet<"vsrl", "csil",
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- [["vv", "Uv", "UvUvUv"],
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- ["vx", "Uv", "UvUvz"]]>;
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- defm vsra : RVVOutOp1BuiltinSet<"vsra", "csil",
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- [["vv", "v", "vvUv"],
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- ["vx", "v", "vvz"]]>;
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+ defm vsll : RVVShiftBuiltinSet;
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+ defm vsrl : RVVUnsignedShiftBuiltinSet;
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+ defm vsra : RVVSignedShiftBuiltinSet;
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// 12.7. Vector Narrowing Integer Right Shift Instructions
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- let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
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- defm vnsrl : RVVOutOp0Op1BuiltinSet<"vnsrl", "csi",
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- [["wv", "Uv", "UvUwUv"],
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- ["wx", "Uv", "UvUwz"]]>;
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- defm vnsra : RVVOutOp0Op1BuiltinSet<"vnsra", "csi",
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- [["wv", "v", "vwUv"],
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- ["wx", "v", "vwz"]]>;
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- }
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+ defm vnsrl : RVVUnsignedNShiftBuiltinSet;
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+ defm vnsra : RVVSignedNShiftBuiltinSet;
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// 12.8. Vector Integer Comparison Instructions
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defm vmseq : RVVIntMaskOutBuiltinSet;
@@ -615,6 +631,30 @@ defm vwmaccus : RVVOutOp1Op2BuiltinSet<"vwmaccus", "csi",
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// 12.16. Vector Integer Move Instructions
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// TODO
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+ // 13. Vector Fixed-Point Arithmetic Instructions
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+ // 13.1. Vector Single-Width Saturating Add and Subtract
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+ defm vsaddu : RVVUnsignedBinBuiltinSet;
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+ defm vsadd : RVVSignedBinBuiltinSet;
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+ defm vssubu : RVVUnsignedBinBuiltinSet;
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+ defm vssub : RVVSignedBinBuiltinSet;
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+
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+ // 13.2. Vector Single-Width Averaging Add and Subtract
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+ defm vaaddu : RVVUnsignedBinBuiltinSet;
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+ defm vaadd : RVVSignedBinBuiltinSet;
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+ defm vasubu : RVVUnsignedBinBuiltinSet;
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+ defm vasub : RVVSignedBinBuiltinSet;
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+
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+ // 13.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
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+ defm vsmul : RVVSignedBinBuiltinSet;
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+
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+ // 13.4. Vector Single-Width Scaling Shift Instructions
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+ defm vssrl : RVVUnsignedShiftBuiltinSet;
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+ defm vssra : RVVSignedShiftBuiltinSet;
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+
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+ // 13.5. Vector Narrowing Fixed-Point Clip Instructions
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+ defm vnclipu : RVVUnsignedNShiftBuiltinSet;
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+ defm vnclip : RVVSignedNShiftBuiltinSet;
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+
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// 14. Vector Floating-Point Instructions
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// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
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defm vfadd : RVVFloatingBinBuiltinSet;
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