@@ -228,6 +228,16 @@ multiclass RVVOutOp1BuiltinSet<string intrinsic_name, string type_range,
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defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1]>;
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}
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+ multiclass RVVOp0Op1BuiltinSet<string intrinsic_name, string type_range,
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+ list<list<string>> suffixes_prototypes> {
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+ defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [0, 1]>;
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+ }
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+
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+ multiclass RVVOutOp1Op2BuiltinSet<string intrinsic_name, string type_range,
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+ list<list<string>> suffixes_prototypes> {
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+ defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1, 2]>;
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+ }
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+
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multiclass RVVSignedBinBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "v", "vvv"],
@@ -253,6 +263,39 @@ multiclass RVVIntTerBuiltinSet {
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["vx", "Uv", "UvUvUeUv"]]>;
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}
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+ multiclass RVVCarryinBuiltinSet {
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+ defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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+ [["vvm", "v", "vvvm"],
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+ ["vxm", "v", "vvem"],
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+ ["vvm", "Uv", "UvUvUvm"],
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+ ["vxm", "Uv", "UvUvUem"]]>;
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+ }
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+
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+ multiclass RVVCarryOutInBuiltinSet<string intrinsic_name> {
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+ defm "" : RVVOp0Op1BuiltinSet<intrinsic_name, "csil",
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+ [["vvm", "vm", "mvvm"],
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+ ["vxm", "vm", "mvem"],
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+ ["vvm", "Uvm", "mUvUvm"],
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+ ["vxm", "Uvm", "mUvUem"]]>;
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+ }
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+
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+ multiclass RVVSignedMaskOutBuiltinSet {
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+ defm "" : RVVOp0Op1BuiltinSet<NAME, "csil",
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+ [["vv", "vm", "mvv"],
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+ ["vx", "vm", "mve"]]>;
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+ }
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+
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+ multiclass RVVUnsignedMaskOutBuiltinSet {
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+ defm "" : RVVOp0Op1BuiltinSet<NAME, "csil",
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+ [["vv", "Uvm", "mUvUv"],
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+ ["vx", "Uvm", "mUvUe"]]>;
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+ }
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+
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+ multiclass RVVIntMaskOutBuiltinSet {
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+ defm "" : RVVSignedMaskOutBuiltinSet;
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+ defm "" : RVVUnsignedMaskOutBuiltinSet;
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+ }
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+
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multiclass RVVFloatingBinBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "fd",
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[["vv", "v", "vvv"],
@@ -460,7 +503,14 @@ let Log2LMUL = [-3, -2, -1, 0] in {
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}
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// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
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- // TODO
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+ let HasMask = false in {
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+ defm vadc : RVVCarryinBuiltinSet;
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+ defm vmadc : RVVCarryOutInBuiltinSet<"vmadc_carry_in">;
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+ defm vmadc : RVVIntMaskOutBuiltinSet;
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+ defm vsbc : RVVCarryinBuiltinSet;
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+ defm vmsbc : RVVCarryOutInBuiltinSet<"vmsbc_borrow_in">;
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+ defm vmsbc : RVVIntMaskOutBuiltinSet;
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+ }
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// 12.5. Vector Bitwise Logical Instructions
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defm vand : RVVIntBinBuiltinSet;
@@ -491,7 +541,16 @@ defm vnsra : RVVOutOp0Op1BuiltinSet<"vnsra", "csi",
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}
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// 12.8. Vector Integer Comparison Instructions
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- // TODO
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+ defm vmseq : RVVIntMaskOutBuiltinSet;
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+ defm vmsne : RVVIntMaskOutBuiltinSet;
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+ defm vmsltu : RVVUnsignedMaskOutBuiltinSet;
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+ defm vmslt : RVVSignedMaskOutBuiltinSet;
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+ defm vmsleu : RVVUnsignedMaskOutBuiltinSet;
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+ defm vmsle : RVVSignedMaskOutBuiltinSet;
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+ defm vmsgtu : RVVOp0Op1BuiltinSet<"vmsgtu", "csil",
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+ [["vx", "Uvm", "mUvUe"]]>;
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+ defm vmsgt : RVVOp0Op1BuiltinSet<"vmsgt", "csil",
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+ [["vx", "vm", "mve"]]>;
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// 12.9. Vector Integer Min/Max Instructions
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defm vminu : RVVUnsignedBinBuiltinSet;
@@ -535,7 +594,20 @@ let HasMaskedOffOperand = false in {
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}
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// 12.14. Vector Widening Integer Multiply-Add Instructions
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- // TODO
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+ let HasMaskedOffOperand = false,
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+ Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
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+ defm vwmaccu : RVVOutOp1Op2BuiltinSet<"vwmaccu", "csi",
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+ [["vv", "Uw", "UwUwUvUv"],
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+ ["vx", "Uw", "UwUwUeUv"]]>;
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+ defm vwmacc : RVVOutOp1Op2BuiltinSet<"vwmacc", "csi",
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+ [["vv", "w", "wwvv"],
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+ ["vx", "w", "wwev"]]>;
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+ defm vwmaccsu : RVVOutOp1Op2BuiltinSet<"vwmaccsu", "csi",
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+ [["vv", "w", "wwvUv"],
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+ ["vx", "w", "wweUv"]]>;
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+ defm vwmaccus : RVVOutOp1Op2BuiltinSet<"vwmaccus", "csi",
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+ [["vx", "w", "wwUev"]]>;
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+ }
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// 12.15. Vector Integer Merge Instructions
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// TODO
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