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Merge pull request stm32duino#1138 from fpistm/Update_L4
Update STM32L4 HAL and CMSIS drivers
2 parents 952fb78 + 1657dfa commit f41f10e

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‎cores/arduino/stm32/usb/usbd_conf.c

+8
Original file line numberDiff line numberDiff line change
@@ -465,7 +465,15 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
465465
USBD_reenumerate();
466466
/* Set common LL Driver parameters */
467467
g_hpcd.Init.dev_endpoints = DEV_NUM_EP;
468+
#ifdef DEP0CTL_MPS_64
468469
g_hpcd.Init.ep0_mps = DEP0CTL_MPS_64;
470+
#else
471+
#ifdef EP_MPS_64
472+
g_hpcd.Init.ep0_mps = EP_MPS_64;
473+
#else
474+
#error "Missing EP0 MPS definition: DEP0CTL_MPS_64 or EP_MPS_64!"
475+
#endif
476+
#endif
469477
#if !defined(STM32F1xx) && !defined(STM32F2xx) || defined(USB)
470478
g_hpcd.Init.lpm_enable = DISABLE;
471479
g_hpcd.Init.battery_charging_enable = DISABLE;

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h

+10-2
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,10 @@
1515
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
1616
* All rights reserved.</center></h2>
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
18+
* This software component is licensed by ST under Apache License, Version 2.0,
1919
* the "License"; You may not use this file except in compliance with the
2020
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
21+
* opensource.org/licenses/Apache-2.0
2222
*
2323
******************************************************************************
2424
*/
@@ -2251,6 +2251,14 @@ typedef struct
22512251
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
22522252
#define CRS_CR_TRIM_Pos (8U)
22532253
#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
2254+
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[6:0] HSI48 oscillator smooth trimming */
2255+
#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */
2256+
#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */
2257+
#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */
2258+
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
2259+
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
2260+
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
2261+
#define CRS_CR_TRIM_6 (0x40UL << CRS_CR_TRIM_Pos) /*!< 0x00004000 */
22542262
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
22552263

22562264
/******************* Bit definition for CRS_CFGR register *********************/

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h

+10-2
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,10 @@
1515
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
1616
* All rights reserved.</center></h2>
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
18+
* This software component is licensed by ST under Apache License, Version 2.0,
1919
* the "License"; You may not use this file except in compliance with the
2020
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
21+
* opensource.org/licenses/Apache-2.0
2222
*
2323
******************************************************************************
2424
*/
@@ -2286,6 +2286,14 @@ typedef struct
22862286
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
22872287
#define CRS_CR_TRIM_Pos (8U)
22882288
#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
2289+
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[6:0] HSI48 oscillator smooth trimming */
2290+
#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */
2291+
#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */
2292+
#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */
2293+
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
2294+
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
2295+
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
2296+
#define CRS_CR_TRIM_6 (0x40UL << CRS_CR_TRIM_Pos) /*!< 0x00004000 */
22892297
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
22902298

22912299
/******************* Bit definition for CRS_CFGR register *********************/

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h

+13-4
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,10 @@
1515
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
1616
* All rights reserved.</center></h2>
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
18+
* This software component is licensed by ST under Apache License, Version 2.0,
1919
* the "License"; You may not use this file except in compliance with the
2020
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
21+
* opensource.org/licenses/Apache-2.0
2222
*
2323
******************************************************************************
2424
*/
@@ -5722,6 +5722,13 @@ typedef struct
57225722
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
57235723
#define CRS_CR_TRIM_Pos (8U)
57245724
#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5725+
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */
5726+
#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */
5727+
#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */
5728+
#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */
5729+
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
5730+
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
5731+
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
57255732
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
57265733

57275734
/******************* Bit definition for CRS_CFGR register *********************/
@@ -9270,13 +9277,15 @@ typedef struct
92709277

92719278
/*!< HSITRIM configuration */
92729279
#define RCC_ICSCR_HSITRIM_Pos (24U)
9273-
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
9274-
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
9280+
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
9281+
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
92759282
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
92769283
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
92779284
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
92789285
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
92799286
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
9287+
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
9288+
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
92809289

92819290
/******************** Bit definition for RCC_CFGR register ******************/
92829291
/*!< SW configuration */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h

+13-4
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,10 @@
1515
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
1616
* All rights reserved.</center></h2>
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
18+
* This software component is licensed by ST under Apache License, Version 2.0,
1919
* the "License"; You may not use this file except in compliance with the
2020
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
21+
* opensource.org/licenses/Apache-2.0
2222
*
2323
******************************************************************************
2424
*/
@@ -5707,6 +5707,13 @@ typedef struct
57075707
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
57085708
#define CRS_CR_TRIM_Pos (8U)
57095709
#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5710+
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */
5711+
#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */
5712+
#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */
5713+
#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */
5714+
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
5715+
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
5716+
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
57105717
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
57115718

57125719
/******************* Bit definition for CRS_CFGR register *********************/
@@ -8931,13 +8938,15 @@ typedef struct
89318938

89328939
/*!< HSITRIM configuration */
89338940
#define RCC_ICSCR_HSITRIM_Pos (24U)
8934-
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
8935-
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
8941+
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
8942+
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
89368943
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
89378944
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
89388945
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
89398946
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
89408947
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
8948+
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
8949+
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
89418950

89428951
/******************** Bit definition for RCC_CFGR register ******************/
89438952
/*!< SW configuration */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h

+13-4
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,10 @@
1515
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
1616
* All rights reserved.</center></h2>
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
18+
* This software component is licensed by ST under Apache License, Version 2.0,
1919
* the "License"; You may not use this file except in compliance with the
2020
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
21+
* opensource.org/licenses/Apache-2.0
2222
*
2323
******************************************************************************
2424
*/
@@ -5781,6 +5781,13 @@ typedef struct
57815781
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
57825782
#define CRS_CR_TRIM_Pos (8U)
57835783
#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5784+
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */
5785+
#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */
5786+
#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */
5787+
#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */
5788+
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
5789+
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
5790+
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
57845791
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
57855792

57865793
/******************* Bit definition for CRS_CFGR register *********************/
@@ -9362,13 +9369,15 @@ typedef struct
93629369

93639370
/*!< HSITRIM configuration */
93649371
#define RCC_ICSCR_HSITRIM_Pos (24U)
9365-
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
9366-
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
9372+
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
9373+
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
93679374
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
93689375
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
93699376
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
93709377
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
93719378
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
9379+
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
9380+
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
93729381

93739382
/******************** Bit definition for RCC_CFGR register ******************/
93749383
/*!< SW configuration */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h

+13-4
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,10 @@
1515
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
1616
* All rights reserved.</center></h2>
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
18+
* This software component is licensed by ST under Apache License, Version 2.0,
1919
* the "License"; You may not use this file except in compliance with the
2020
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
21+
* opensource.org/licenses/Apache-2.0
2222
*
2323
******************************************************************************
2424
*/
@@ -5742,6 +5742,13 @@ typedef struct
57425742
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
57435743
#define CRS_CR_TRIM_Pos (8U)
57445744
#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5745+
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */
5746+
#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */
5747+
#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */
5748+
#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */
5749+
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
5750+
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
5751+
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
57455752
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
57465753

57475754
/******************* Bit definition for CRS_CFGR register *********************/
@@ -9147,13 +9154,15 @@ typedef struct
91479154

91489155
/*!< HSITRIM configuration */
91499156
#define RCC_ICSCR_HSITRIM_Pos (24U)
9150-
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
9151-
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
9157+
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
9158+
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
91529159
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
91539160
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
91549161
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
91559162
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
91569163
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
9164+
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
9165+
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
91579166

91589167
/******************** Bit definition for RCC_CFGR register ******************/
91599168
/*!< SW configuration */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h

+13-4
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,10 @@
1515
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
1616
* All rights reserved.</center></h2>
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
18+
* This software component is licensed by ST under Apache License, Version 2.0,
1919
* the "License"; You may not use this file except in compliance with the
2020
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
21+
* opensource.org/licenses/Apache-2.0
2222
*
2323
******************************************************************************
2424
*/
@@ -5816,6 +5816,13 @@ typedef struct
58165816
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
58175817
#define CRS_CR_TRIM_Pos (8U)
58185818
#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5819+
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */
5820+
#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */
5821+
#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */
5822+
#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */
5823+
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
5824+
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
5825+
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
58195826
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
58205827

58215828
/******************* Bit definition for CRS_CFGR register *********************/
@@ -9578,13 +9585,15 @@ typedef struct
95789585

95799586
/*!< HSITRIM configuration */
95809587
#define RCC_ICSCR_HSITRIM_Pos (24U)
9581-
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
9582-
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
9588+
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
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#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
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#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
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#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
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#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
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#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
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#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
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#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
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#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
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/******************** Bit definition for RCC_CFGR register ******************/
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/*!< SW configuration */

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