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Merge pull request stm32duino#1137 from fpistm/Update_G4
Update STM32G4 HAL and CMSIS drivers
2 parents b9f2434 + 9cc22c7 commit 952fb78

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137 files changed

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‎cores/arduino/stm32/stm32_def_build.h

+4
Original file line numberDiff line numberDiff line change
@@ -198,6 +198,10 @@
198198
#define CMSIS_STARTUP_FILE "startup_stm32g483xx.s"
199199
#elif defined(STM32G484xx)
200200
#define CMSIS_STARTUP_FILE "startup_stm32g484xx.s"
201+
#elif defined(STM32G491xx)
202+
#define CMSIS_STARTUP_FILE "startup_stm32g491xx.s"
203+
#elif defined(STM32G4A1xx)
204+
#define CMSIS_STARTUP_FILE "startup_stm32g4a1xx.s"
201205
#elif defined(STM32GBK1CB)
202206
#define CMSIS_STARTUP_FILE "startup_stm32gbk1cb.s"
203207
#elif defined(STM32H742xx)

‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h

+5-15
Original file line numberDiff line numberDiff line change
@@ -1438,10 +1438,6 @@ typedef struct
14381438
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
14391439
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
14401440

1441-
#define ADC_CFGR2_LFTRIG_Pos (29U)
1442-
#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
1443-
#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */
1444-
14451441
/******************** Bit definition for ADC_SMPR1 register *****************/
14461442
#define ADC_SMPR1_SMP0_Pos (0U)
14471443
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
@@ -2228,11 +2224,11 @@ typedef struct
22282224

22292225
#define COMP_CSR_BRGEN_Pos (22U)
22302226
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
2231-
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
2227+
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
22322228

22332229
#define COMP_CSR_SCALEN_Pos (23U)
22342230
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
2235-
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
2231+
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
22362232

22372233
#define COMP_CSR_VALUE_Pos (30U)
22382234
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
@@ -2303,7 +2299,6 @@ typedef struct
23032299
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
23042300
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
23052301

2306-
23072302
/******************************************************************************/
23082303
/* */
23092304
/* CRC calculation unit */
@@ -2452,9 +2447,9 @@ typedef struct
24522447
/* */
24532448
/******************************************************************************/
24542449
/*
2455-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
2450+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
24562451
*/
2457-
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
2452+
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
24582453

24592454
/******************** Bit definition for DAC_CR register ********************/
24602455
#define DAC_CR_EN1_Pos (0U)
@@ -2658,7 +2653,6 @@ typedef struct
26582653
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
26592654
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
26602655

2661-
26622656
#define DAC_SR_DAC2RDY_Pos (27U)
26632657
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
26642658
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
@@ -2874,7 +2868,6 @@ typedef struct
28742868
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
28752869
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
28762870

2877-
/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
28782871

28792872
/******************** Bit definition for DBGMCU_APB2FZ register ************/
28802873
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
@@ -9932,6 +9925,7 @@ typedef struct
99329925
#define SYSCFG_SWPR_PAGE9_Pos (9U)
99339926
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
99349927
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
9928+
99359929
/****************** Bit definition for SYSCFG_SKR register ****************/
99369930
#define SYSCFG_SKR_KEY_Pos (0U)
99379931
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -12538,7 +12532,6 @@ typedef struct
1253812532
*/
1253912533

1254012534
/******************************* ADC Instances ********************************/
12541-
1254212535
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
1254312536
((INSTANCE) == ADC2))
1254412537

@@ -12618,7 +12611,6 @@ typedef struct
1261812611
((INSTANCE) == OPAMP2) || \
1261912612
((INSTANCE) == OPAMP3))
1262012613

12621-
1262212614
/******************************** PCD Instances *******************************/
1262312615
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
1262412616

@@ -12945,7 +12937,6 @@ typedef struct
1294512937
((INSTANCE) == TIM15))
1294612938

1294712939
/****************** TIM Instances : supporting OCxREF clear *******************/
12948-
1294912940
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1295012941
((INSTANCE) == TIM2) || \
1295112942
((INSTANCE) == TIM3) || \
@@ -13000,7 +12991,6 @@ typedef struct
1300012991
((INSTANCE) == TIM16) || \
1300112992
((INSTANCE) == TIM17))
1300212993

13003-
1300412994
/****************** TIM Instances : Advanced timer instances *******************/
1300512995
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1300612996
((INSTANCE) == TIM8))

‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g441xx.h

+5-16
Original file line numberDiff line numberDiff line change
@@ -1472,10 +1472,6 @@ typedef struct
14721472
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
14731473
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
14741474

1475-
#define ADC_CFGR2_LFTRIG_Pos (29U)
1476-
#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
1477-
#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */
1478-
14791475
/******************** Bit definition for ADC_SMPR1 register *****************/
14801476
#define ADC_SMPR1_SMP0_Pos (0U)
14811477
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
@@ -2407,7 +2403,6 @@ typedef struct
24072403
#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */
24082404
#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */
24092405

2410-
24112406
/******************************************************************************/
24122407
/* */
24132408
/* Analog Comparators (COMP) */
@@ -2450,11 +2445,11 @@ typedef struct
24502445

24512446
#define COMP_CSR_BRGEN_Pos (22U)
24522447
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
2453-
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
2448+
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
24542449

24552450
#define COMP_CSR_SCALEN_Pos (23U)
24562451
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
2457-
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
2452+
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
24582453

24592454
#define COMP_CSR_VALUE_Pos (30U)
24602455
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
@@ -2525,7 +2520,6 @@ typedef struct
25252520
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
25262521
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
25272522

2528-
25292523
/******************************************************************************/
25302524
/* */
25312525
/* CRC calculation unit */
@@ -2674,9 +2668,9 @@ typedef struct
26742668
/* */
26752669
/******************************************************************************/
26762670
/*
2677-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
2671+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
26782672
*/
2679-
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
2673+
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
26802674

26812675
/******************** Bit definition for DAC_CR register ********************/
26822676
#define DAC_CR_EN1_Pos (0U)
@@ -2880,7 +2874,6 @@ typedef struct
28802874
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
28812875
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
28822876

2883-
28842877
#define DAC_SR_DAC2RDY_Pos (27U)
28852878
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
28862879
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
@@ -3096,7 +3089,6 @@ typedef struct
30963089
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
30973090
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
30983091

3099-
/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
31003092

31013093
/******************** Bit definition for DBGMCU_APB2FZ register ************/
31023094
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
@@ -10163,6 +10155,7 @@ typedef struct
1016310155
#define SYSCFG_SWPR_PAGE9_Pos (9U)
1016410156
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
1016510157
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
10158+
1016610159
/****************** Bit definition for SYSCFG_SKR register ****************/
1016710160
#define SYSCFG_SKR_KEY_Pos (0U)
1016810161
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -12769,7 +12762,6 @@ typedef struct
1276912762
*/
1277012763

1277112764
/******************************* ADC Instances ********************************/
12772-
1277312765
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
1277412766
((INSTANCE) == ADC2))
1277512767

@@ -12851,7 +12843,6 @@ typedef struct
1285112843
((INSTANCE) == OPAMP2) || \
1285212844
((INSTANCE) == OPAMP3))
1285312845

12854-
1285512846
/******************************** PCD Instances *******************************/
1285612847
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
1285712848

@@ -13178,7 +13169,6 @@ typedef struct
1317813169
((INSTANCE) == TIM15))
1317913170

1318013171
/****************** TIM Instances : supporting OCxREF clear *******************/
13181-
1318213172
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1318313173
((INSTANCE) == TIM2) || \
1318413174
((INSTANCE) == TIM3) || \
@@ -13233,7 +13223,6 @@ typedef struct
1323313223
((INSTANCE) == TIM16) || \
1323413224
((INSTANCE) == TIM17))
1323513225

13236-
1323713226
/****************** TIM Instances : Advanced timer instances *******************/
1323813227
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1323913228
((INSTANCE) == TIM8))

‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g471xx.h

+5-14
Original file line numberDiff line numberDiff line change
@@ -1502,10 +1502,6 @@ typedef struct
15021502
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
15031503
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
15041504

1505-
#define ADC_CFGR2_LFTRIG_Pos (29U)
1506-
#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
1507-
#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */
1508-
15091505
/******************** Bit definition for ADC_SMPR1 register *****************/
15101506
#define ADC_SMPR1_SMP0_Pos (0U)
15111507
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
@@ -2292,11 +2288,11 @@ typedef struct
22922288

22932289
#define COMP_CSR_BRGEN_Pos (22U)
22942290
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
2295-
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
2291+
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
22962292

22972293
#define COMP_CSR_SCALEN_Pos (23U)
22982294
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
2299-
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
2295+
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
23002296

23012297
#define COMP_CSR_VALUE_Pos (30U)
23022298
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
@@ -2367,7 +2363,6 @@ typedef struct
23672363
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
23682364
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
23692365

2370-
23712366
/******************************************************************************/
23722367
/* */
23732368
/* CRC calculation unit */
@@ -2516,9 +2511,9 @@ typedef struct
25162511
/* */
25172512
/******************************************************************************/
25182513
/*
2519-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
2514+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
25202515
*/
2521-
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
2516+
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
25222517

25232518
/******************** Bit definition for DAC_CR register ********************/
25242519
#define DAC_CR_EN1_Pos (0U)
@@ -2722,7 +2717,6 @@ typedef struct
27222717
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
27232718
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
27242719

2725-
27262720
#define DAC_SR_DAC2RDY_Pos (27U)
27272721
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
27282722
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
@@ -10440,6 +10434,7 @@ typedef struct
1044010434
#define SYSCFG_SWPR_PAGE31_Pos (31U)
1044110435
#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
1044210436
#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
10437+
1044310438
/****************** Bit definition for SYSCFG_SKR register ****************/
1044410439
#define SYSCFG_SKR_KEY_Pos (0U)
1044510440
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -13056,7 +13051,6 @@ typedef struct
1305613051
((INSTANCE) == ADC345_COMMON) )
1305713052

1305813053

13059-
1306013054
/******************************** FDCAN Instances ******************************/
1306113055
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
1306213056
((INSTANCE) == FDCAN2))
@@ -13134,7 +13128,6 @@ typedef struct
1313413128
((INSTANCE) == OPAMP2) || \
1313513129
((INSTANCE) == OPAMP3))
1313613130

13137-
1313813131
/******************************** PCD Instances *******************************/
1313913132
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
1314013133

@@ -13500,7 +13493,6 @@ typedef struct
1350013493
((INSTANCE) == TIM16) || \
1350113494
((INSTANCE) == TIM17))
1350213495

13503-
1350413496
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
1350513497
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1350613498
((INSTANCE) == TIM2) || \
@@ -13549,7 +13541,6 @@ typedef struct
1354913541
((INSTANCE) == TIM16) || \
1355013542
((INSTANCE) == TIM17))
1355113543

13552-
1355313544
/****************** TIM Instances : Advanced timer instances *******************/
1355413545
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1355513546
((INSTANCE) == TIM8))

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