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Olimex boards ESP32-EVB/Gateway ethernet fix #6188

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Olimex boards ESP32-EVB/Gateway ethernet fix #6188

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8 changes: 4 additions & 4 deletions boards.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -5550,11 +5550,11 @@ esp32-gateway.build.core=esp32
esp32-gateway.build.variant=esp32-gateway
esp32-gateway.build.board=ESP32_GATEWAY
esp32-gateway.menu.Revision.RevC=Revision C or older
esp32-gateway.menu.Revision.RevC.build.board=ESP32_GATEWAY_C
esp32-gateway.menu.Revision.RevC.build.board=ESP32_GATEWAY='C'
esp32-gateway.menu.Revision.RevE=Revision E
esp32-gateway.menu.Revision.RevE.build.board=ESP32_GATEWAY_E
esp32-gateway.menu.Revision.RevF=Revision F
esp32-gateway.menu.Revision.RevF.build.board=ESP32_GATEWAY_F
esp32-gateway.menu.Revision.RevE.build.board=ESP32_GATEWAY='E'
esp32-gateway.menu.Revision.RevF=Revision F or newer
esp32-gateway.menu.Revision.RevF.build.board=ESP32_GATEWAY='F'

esp32-gateway.build.f_cpu=240000000L
esp32-gateway.build.flash_mode=dio
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3 changes: 3 additions & 0 deletions libraries/Ethernet/src/ETH.cpp
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Expand Up @@ -228,6 +228,9 @@ ETHClass::~ETHClass()

bool ETHClass::begin(uint8_t phy_addr, int power, int mdc, int mdio, eth_phy_type_t type, eth_clock_mode_t clock_mode)
{
#if defined ARDUINO_ESP32_EVB
delay (350); // Olimex board ESP32-EVB requires short delay before the phy initialization after reset
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Doesn't it make more sense to check the clock mode?
If the clock mode is external crystal on GPIO-0, then this should apply.

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@sauttefk sauttefk Jan 25, 2022 •
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no, this is just the very long 470ms delay on this particular board and how this is implemented to save a GPIO pin

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470 ms?
The change mentions 350 ms

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470ms is the RC-time constant of the supervisor chip, that enables the PHY-clock.
The ESP32 has also an RC-reset circuit with 100ms delay.
So 470ms - 100ms = 370ms. Plus the startup time the ESP32 take until it reaches the code, where the Ethernet is being configured.

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Hmm that sounds awfully critical timed and extremely board specific.
Tolerances of capacitors are quite big (tens of percent), and capacity of a capacitor may reduce over time as the component ages.

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Hey and sorry for the late reply. I didn't expect such an interest considering I posted an issue about a week ago but there was only one suggestion there, so I thought it would take days (if at all) before this pull request is discussed.

Anyway - for the issue I thought it is something specific for ESP32-EVB board and with colleagues after some testing we figured that this solves the issue. Although it's more of a workaround rather than an actual fix. We are not aware if other boards will need it or not.

The value for the delay is empirically derived by testing about 20 of our boards. Some of which behaved properly and the sketch worked as intended with or without the delay. While others needed between 100-250 ms to make it work at all. The most demanding boards required ~275ms at which point sometimes they sometimes worked, sometimes failed. And at 300 I didn't find any that aren't working. The extra 50 ms on top of that are more of a "insurance" although you might be right that it will need more.

As for the suggestion with the clock mode check - what exactly do you mean? I knew my solution (or should I say workaround) is lame but considering it get the job done I decided it's better than not having it at all. I am open for suggestions in that regard. It's just that I am uncertain how to implement a more elegant solution.

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Regarding the clock mode.
There are 2 configuration related issues here:

  • The need to power manage (or reset) the LAN controller
  • Whether or not there is an actual need for blocking a clock signal to GPIO-0

Resetting the LAN controller via the reset pin needs roughly 100 msec for the LAN controller to properly work.
Power cycling the LAN controller can be useful for saving power (it needs 40 - 100 mA, depending on whether it is connected to a switch). This can also be used to suppress any clock signal to GPIO-0 when using an external crystal.
Depending on the power supply and R/C timings this may take a few-100 msec to get stable + the 100 msec as with performing a reset.
Blocking a clock signal to GPIO-0 can be handled with an analog switch chip or holding down the EN pin of the crystal.
Switching this takes a few msec at most (when toggling the EN pin of the crystal).

If the clock mode is set to have an external crystal, then it is likely the power pin is either used for power cycling the LAN controller and/or switching the clock signal to GPIO-0. I assume most boards will power cycle the LAN controller as this also can be used as a reset to clear any unrecoverable error state on the LAN controller (which does happen every now and then)

Thus having either the PWR or RST pin set, or the clock mode set to GPIO-0 external crystal, can be used to add some extra delay.

#endif
#if ESP_IDF_VERSION_MAJOR > 3
eth_clock_mode = clock_mode;
tcpipInit();
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