cores/esp8266/core_esp8266_features.cpp: Make precache() cleaner and more efficient #8903
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…more efficient
No need to issue a MEMW instrunction per load from each cache line.
Only once after the last load is sufficient.
MEMW ensures that all previous load, store, acquire, release, prefetch,
and cache instructions perform before performing any subsequent load,
store, acquire, release, prefetch, or cache instructions.
-- MEMW (Memory Wait), 6. Instruction Descriptions,
Xtensa ISA Reference Manual (p.409)
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No need to issue a MEMW instrunction per load from each cache line.
Only once after the last load is sufficient.
MEMW ensures that all previous load, store, acquire, release, prefetch,
and cache instructions perform before performing any subsequent load,
store, acquire, release, prefetch, or cache instructions.
-- MEMW (Memory Wait), 6. Instruction Descriptions,
Xtensa ISA Reference Manual (p.409)
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No need to issue a MEMW instrunction per load from each cache line. Only once after the last load is sufficient.