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Merge pull request #704 from diffblue/smv-iff
SMV: use `ID_smv_iff` for `<->`
2 parents 8cce1ce + 51b70df commit fd6f656

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12 files changed

+69
-14
lines changed

12 files changed

+69
-14
lines changed

regression/ebmc/smv/smv_iff1.desc

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
CORE
2+
smv_iff1.smv
3+
4+
^file .* line 9: Expected expression of type `boolean', but got expression `x', which is of type `0..10'$
5+
^EXIT=2$
6+
^SIGNAL=0$
7+
--

regression/ebmc/smv/smv_iff1.smv

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
MODULE main
2+
3+
VAR x : 0..10;
4+
5+
ASSIGN init(x) := 1;
6+
next(x) := x;
7+
8+
-- type error: lhs is not Boolean
9+
SPEC x <-> (x != 0)

regression/ebmc/smv/smv_iff2.desc

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
CORE
2+
smv_iff2.smv
3+
--bdd
4+
^\[.*\] \(AG x != 5\) <-> \(x != 5 & AX AG x != 5\): PROVED$
5+
^EXIT=0$
6+
^SIGNAL=0$
7+
--

regression/ebmc/smv/smv_iff2.smv

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
MODULE main
2+
3+
VAR x : 0..10;
4+
5+
ASSIGN
6+
init(x) := 1;
7+
8+
next(x) :=
9+
case
10+
x>=3 : 3;
11+
TRUE: x+1;
12+
esac;
13+
14+
SPEC AG x != 5 <-> (x != 5 & AX AG x != 5)

src/ebmc/bdd_engine.cpp

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -673,6 +673,12 @@ bdd_enginet::BDD bdd_enginet::CTL(const exprt &expr)
673673
result = result | CTL(op);
674674
return result;
675675
}
676+
else if(
677+
expr.id() == ID_equal && to_equal_expr(expr).lhs().type().id() == ID_bool)
678+
{
679+
return (
680+
!(CTL(to_binary_expr(expr).lhs())) ^ CTL(to_binary_expr(expr).rhs()));
681+
}
676682
else if(expr.id() == ID_EX)
677683
{
678684
return EX(CTL(to_EX_expr(expr).op()));
@@ -891,7 +897,10 @@ void bdd_enginet::get_atomic_propositions(const exprt &expr)
891897
{
892898
if(
893899
expr.id() == ID_and || expr.id() == ID_or || expr.id() == ID_not ||
894-
expr.id() == ID_implies || is_temporal_operator(expr))
900+
expr.id() == ID_implies ||
901+
(expr.id() == ID_equal &&
902+
to_equal_expr(expr).lhs().type().id() == ID_bool) ||
903+
is_temporal_operator(expr))
895904
{
896905
for(const auto & op : expr.operands())
897906
if(op.type().id() == ID_bool)

src/hw_cbmc_irep_ids.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@ IREP_ID_ONE(F)
1515
IREP_ID_ONE(E)
1616
IREP_ID_ONE(G)
1717
IREP_ID_ONE(X)
18+
IREP_ID_ONE(smv_iff)
19+
IREP_ID_TWO(C_smv_iff, "#smv_iff")
1820
IREP_ID_ONE(sva_accept_on)
1921
IREP_ID_ONE(sva_reject_on)
2022
IREP_ID_ONE(sva_sync_accept_on)
@@ -215,7 +217,7 @@ IREP_ID_ONE(verilog_ref)
215217
IREP_ID_ONE(verilog_reg)
216218
IREP_ID_ONE(verilog_integer)
217219
IREP_ID_ONE(verilog_time)
218-
IREP_ID_ONE(iff)
220+
IREP_ID_ONE(verilog_iff)
219221
IREP_ID_ONE(offset)
220222
IREP_ID_ONE(xnor)
221223
IREP_ID_ONE(specify)

src/smvlang/expr2smv.cpp

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -449,7 +449,12 @@ bool expr2smvt::convert(
449449
return convert_binary(src, dest, src.id_string(), precedence=11);
450450

451451
else if(src.id()==ID_equal)
452-
return convert_binary(src, dest, "=", precedence=11);
452+
{
453+
if(src.get_bool(ID_C_smv_iff))
454+
return convert_binary(src, dest, "<->", precedence = 16);
455+
else
456+
return convert_binary(src, dest, "=", precedence = 11);
457+
}
453458

454459
else if(src.id()==ID_notequal)
455460
return convert_binary(src, dest, "!=", precedence=11);
@@ -466,9 +471,6 @@ bool expr2smvt::convert(
466471
else if(src.id()==ID_implies)
467472
return convert_binary(src, dest, "->", precedence=2);
468473

469-
else if(src.id()==ID_iff)
470-
return convert_binary(src, dest, "<->", precedence=3);
471-
472474
else if(
473475
src.id() == ID_AG || src.id() == ID_EG || src.id() == ID_AF ||
474476
src.id() == ID_EF || src.id() == ID_AX || src.id() == ID_EX ||

src/smvlang/parser.y

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -455,7 +455,7 @@ term : variable_name
455455
| term DIVIDE_Token term { binary_arith($$, $1, ID_div, $3); }
456456
| term PLUS_Token term { binary_arith($$, $1, ID_plus, $3); }
457457
| term MINUS_Token term { binary_arith($$, $1, ID_minus, $3); }
458-
| term EQUIV_Token term { binary($$, $1, ID_equal, $3, bool_typet{}); }
458+
| term EQUIV_Token term { binary($$, $1, ID_smv_iff, $3, bool_typet{}); }
459459
| term IMPLIES_Token term { binary($$, $1, ID_implies, $3, bool_typet{}); }
460460
| term XOR_Token term { j_binary($$, $1, ID_xor, $3, bool_typet{}); }
461461
| term OR_Token term { j_binary($$, $1, ID_or, $3, bool_typet{}); }

src/smvlang/smv_typecheck.cpp

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -681,12 +681,17 @@ void smv_typecheckt::typecheck(
681681
}
682682
}
683683
}
684-
else if(expr.id()==ID_and ||
685-
expr.id()==ID_or ||
686-
expr.id()==ID_xor ||
687-
expr.id()==ID_not)
684+
else if(
685+
expr.id() == ID_and || expr.id() == ID_or || expr.id() == ID_xor ||
686+
expr.id() == ID_not)
687+
{
688+
typecheck_op(expr, bool_typet(), mode);
689+
}
690+
else if(expr.id() == ID_smv_iff)
688691
{
689692
typecheck_op(expr, bool_typet(), mode);
693+
expr.set(ID_C_smv_iff, true);
694+
expr.id(ID_equal);
690695
}
691696
else if(expr.id()==ID_nondet_symbol)
692697
{

src/verilog/expr2verilog.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1337,7 +1337,7 @@ expr2verilogt::resultt expr2verilogt::convert_rec(const exprt &src)
13371337
return convert_binary(
13381338
to_multi_ary_expr(src), "->", precedence = verilog_precedencet::IMPLIES);
13391339

1340-
else if(src.id()==ID_iff)
1340+
else if(src.id() == ID_verilog_iff)
13411341
return convert_binary(
13421342
to_multi_ary_expr(src), "<->", precedence = verilog_precedencet::IMPLIES);
13431343

src/verilog/parser.y

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3534,7 +3534,7 @@ expression:
35343534
| expression "->" expression
35353535
{ init($$, ID_implies); mto($$, $1); mto($$, $3); }
35363536
| expression "<->" expression
3537-
{ init($$, ID_iff); mto($$, $1); mto($$, $3); }
3537+
{ init($$, ID_verilog_iff); mto($$, $1); mto($$, $3); }
35383538
| expression TOK_PLUS expression
35393539
{ init($$, ID_plus); mto($$, $1); mto($$, $3); }
35403540
| expression TOK_MINUS expression

src/verilog/verilog_typecheck_expr.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2644,7 +2644,7 @@ exprt verilog_typecheck_exprt::convert_binary_expr(binary_exprt expr)
26442644
else if(expr.id()==ID_replication)
26452645
return convert_replication_expr(to_replication_expr(expr));
26462646
else if(
2647-
expr.id() == ID_and || expr.id() == ID_or || expr.id() == ID_iff ||
2647+
expr.id() == ID_and || expr.id() == ID_or || expr.id() == ID_verilog_iff ||
26482648
expr.id() == ID_implies)
26492649
{
26502650
Forall_operands(it, expr)

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