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Verilog: KNOWNBUG test for recursive module instantiation
Since Verilog 2005 recursive module instantiation is explicitly allowed. This adds a KNOWNBUG test for this.
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KNOWNBUG
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decoder1.sv
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^EXIT=0$
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^SIGNAL=0$
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--
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--
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No support for recursive module dependencies.
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// Example of a recursive module instantiation
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module decoder#(parameter N = 4) (input [N-1:0] binary, output [2**N-1:0] unary);
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generate
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if(N==1)
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assign unary = binary;
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else begin
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// generate one N-1 bit decoder recursively
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wire [2**(N-1)-1:0] output_rec;
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decoder #(N-1) decoder_rec(binary[N-2:0], output_rec);
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wire top = binary[N-1];
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assign unary = {output_rec & {2**(N-1){top}}, output_rec & {2**(N-1){!top}}};
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end
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endgenerate
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endmodule
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module decoder_tb;
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wire [15:0] unary;
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decoder decoder1(4'd5, unary);
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p0: assert final (unary == 'b0000_0000_0001_0000); // 16
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endmodule

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