Verilog: KNOWNBUG test for property ... endproperty

The type checker uses the wrong fragement of the expression syntax for
property ...  endproperty.

Replicates #931.

Author: kroening

regression/verilog/SVA/named_property1.desc renamed to regression/verilog/property/named_property1.desc

@@ -0,0 +1,11 @@
+KNOWNBUG
+named_property2.sv
+--bound 20
+^\[main\.assert\.1\] always main\.x_is_eventually_ten: PROVED up to bound 20$
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The type checker only allows expressions, not properties in property ...
+endproperty.

regression/verilog/SVA/named_property1.sv renamed to regression/verilog/property/named_property1.sv

@@ -0,0 +1,12 @@
+module main(input clk);
+
+  reg [31:0] x = 0;
+  always_ff @(posedge clk) x++;
+
+  property x_is_eventually_ten;
+    s_eventually x == 10
+  endproperty : x_is_eventually_ten
+
+  assert property (x_is_eventually_ten);
+
+endmodule