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Merge pull request #247 from diffblue/convert_integer_constant_expression_source_location
Verilog: preserve a source location when converting elaboration-time constants
2 parents 9cfceac + d78d6a3 commit 9967bb2

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src/verilog/verilog_typecheck_expr.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1131,14 +1131,17 @@ verilog_typecheck_exprt::convert_integer_constant_expression(exprt expr)
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{
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convert_expr(expr);
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1134+
// copy the source location, we will modify 'expr'
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auto source_location = expr.source_location();
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// this could be large
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propagate_type(expr, integer_typet());
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exprt tmp = elaborate_constant_expression(expr);
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if(!tmp.is_constant())
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{
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throw errort().with_location(expr.source_location())
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throw errort().with_location(source_location)
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<< "expected constant expression, but got `" << to_string(tmp) << '\'';
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}
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@@ -1153,7 +1156,7 @@ verilog_typecheck_exprt::convert_integer_constant_expression(exprt expr)
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auto value_opt = numeric_cast<mp_integer>(tmp_constant);
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if(!value_opt.has_value())
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{
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throw errort().with_location(expr.source_location())
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throw errort().with_location(source_location)
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<< "failed to convert `" << to_string(tmp_constant)
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<< "\' into an integer constant";
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}

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