Merge pull request #946 from diffblue/task_invocation1

Verilog: KNOWNBUG test for task invocation without parentheses

Author: tautschnig

regression/verilog/tasks/task_invocation1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+task_invocation1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The parser rejects invocations without ().

regression/verilog/tasks/task_invocation1.sv

@@ -0,0 +1,12 @@
+module top(output reg [31:0] y);
+
+  task my_task;
+    y=123;
+  endtask
+
+  // the parentheses are optional
+  always_comb my_task;
+
+  assert final (y==123);
+
+endmodule