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1 parent 81b3d8e commit 735131cCopy full SHA for 735131c
CHANGELOG
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+# EBMC 5.2
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+* SystemVerilog: defines can now be set on the command line
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+* SystemVerilog: improvements to elaboration-time constant folding
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+* SystemVerilog: continuous assignments to variables
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+* SystemVerilog: additional SVA operators
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+* SystemVerilog: wildcard equality and inequality operators
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+* SystemVerilog: restrict
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+* word-level BMC supports full LTL
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+* SMV: LTL U and R
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+* SMV: ?: operator
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# EBMC 5.1
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* SVA abort properties and disable iff
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