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Merge pull request #616 from diffblue/sequence-repetition
SystemVerilog: sequence repetition operators
2 parents e77063c + ddef850 commit 2dc4c9e

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6 files changed

+110
-4
lines changed

6 files changed

+110
-4
lines changed
Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
KNOWNBUG
2+
sequence_repetition1.sv
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--bound 10
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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currently not implemented
Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
module main(input clk);
2+
3+
reg [31:0] x = 0;
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5+
// 0 1 2 3 4 ...
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always_ff @(posedge clk)
7+
x<=x+1;
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9+
// 0 0 1 1 2 2 3 3 ...
10+
wire [31:0] half_x = x/2;
11+
12+
// should pass
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initial p0: assert property (half_x==0[*2]);
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initial p1: assert property (half_x==0[->2]);
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initial p2: assert property (half_x==0[=2]);
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// should fail
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initial p3: assert property (x==0[*2]);
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initial p4: assert property (x==0[->2]);
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initial p5: assert property (x==0[=2]);
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22+
endmodule

src/hw_cbmc_irep_ids.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,13 @@ IREP_ID_ONE(sva_cycle_delay)
2323
IREP_ID_ONE(sva_cycle_delay_star)
2424
IREP_ID_ONE(sva_cycle_delay_plus)
2525
IREP_ID_ONE(sva_sequence_concatenation)
26+
IREP_ID_ONE(sva_sequence_consecutive_repetition)
2627
IREP_ID_ONE(sva_sequence_first_match)
28+
IREP_ID_ONE(sva_sequence_goto_repetition)
2729
IREP_ID_ONE(sva_sequence_intersect)
30+
IREP_ID_ONE(sva_sequence_non_consecutive_repetition)
31+
IREP_ID_ONE(sva_sequence_repetition_star)
32+
IREP_ID_ONE(sva_sequence_repetition_plus)
2833
IREP_ID_ONE(sva_sequence_throughout)
2934
IREP_ID_ONE(sva_sequence_within)
3035
IREP_ID_ONE(sva_always)

src/verilog/parser.y

Lines changed: 44 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -375,6 +375,10 @@ int yyverilogerror(const char *error)
375375
%token TOK_HASHMINUSHASH "#-#"
376376
%token TOK_HASHEQUALHASH "#=#"
377377
%token TOK_COLONCOLON "::"
378+
%token TOK_LSQASTERIC "[*"
379+
%token TOK_LSQPLUS "[+"
380+
%token TOK_LSQEQUAL "[="
381+
%token TOK_LSQMINUSGREATER "[->"
378382

379383
/* System Verilog Keywords */
380384
%token TOK_ACCEPT_ON "accept_on"
@@ -538,7 +542,7 @@ int yyverilogerror(const char *error)
538542
%left "and"
539543
%nonassoc "not" "nexttime" "s_nexttime"
540544
%left "##"
541-
%nonassoc "[*]" "[=]" "[->]"
545+
%nonassoc "[*" "[=" "[->"
542546

543547
// Precendence of Verilog operators,
544548
// following System Verilog 1800-2017 Table 11-2.
@@ -2184,7 +2188,9 @@ expression_or_dist_brace:
21842188
;
21852189

21862190
sequence_expr:
2187-
expression
2191+
expression_or_dist
2192+
| expression_or_dist boolean_abbrev
2193+
{ $$ = $2; mto($$, $1); }
21882194
| cycle_delay_range sequence_expr
21892195
{ $$=$1; mto($$, $2); }
21902196
| expression cycle_delay_range sequence_expr
@@ -2199,17 +2205,51 @@ sequence_expr:
21992205
{ init($$, ID_sva_sequence_within); mto($$, $1); mto($$, $3); }
22002206
;
22012207

2208+
boolean_abbrev:
2209+
consecutive_repetition
2210+
| non_consecutive_repetition
2211+
| goto_repetition
2212+
;
2213+
2214+
sequence_abbrev:
2215+
consecutive_repetition
2216+
;
2217+
2218+
consecutive_repetition:
2219+
"[*" const_or_range_expression ']'
2220+
{ init($$, ID_sva_sequence_consecutive_repetition); mto($$, $2); }
2221+
| "[*" ']'
2222+
{ init($$, ID_sva_sequence_repetition_star); }
2223+
| "[+" ']'
2224+
{ init($$, ID_sva_sequence_repetition_plus); }
2225+
;
2226+
2227+
non_consecutive_repetition:
2228+
"[=" const_or_range_expression ']'
2229+
{ init($$, ID_sva_sequence_non_consecutive_repetition); mto($$, $2); }
2230+
;
2231+
2232+
goto_repetition:
2233+
"[->" const_or_range_expression ']'
2234+
{ init($$, ID_sva_sequence_goto_repetition); mto($$, $2); }
2235+
;
2236+
22022237
cycle_delay_range:
22032238
"##" number
22042239
{ init($$, ID_sva_cycle_delay); mto($$, $2); stack_expr($$).operands().push_back(nil_exprt()); }
22052240
| "##" '[' cycle_delay_const_range_expression ']'
22062241
{ $$ = $3; }
2207-
| "##" '[' TOK_ASTERIC ']'
2242+
| "##" "[*" ']'
22082243
{ init($$, ID_sva_cycle_delay_star); }
2209-
| "##" '[' TOK_PLUS ']'
2244+
| "##" "[+" ']'
22102245
{ init($$, ID_sva_cycle_delay_plus); }
22112246
;
22122247

2248+
const_or_range_expression:
2249+
constant_expression
2250+
| cycle_delay_const_range_expression
2251+
;
2252+
22132253
cycle_delay_const_range_expression:
22142254
constant_expression TOK_COLON constant_expression
22152255
{ init($$, ID_sva_cycle_delay); mto($$, $1); mto($$, $3); }

src/verilog/scanner.l

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -264,6 +264,11 @@ void verilog_scanner_init()
264264
"->" { SYSTEM_VERILOG_OPERATOR(TOK_MINUSGREATER, "->"); }
265265
"'" { SYSTEM_VERILOG_OPERATOR('\'', "'"); }
266266
"::" { SYSTEM_VERILOG_OPERATOR(TOK_COLONCOLON, "::"); }
267+
/* Table 16-1 in 1800-2017 suggests the following tokens for sequence operators */
268+
"[*" { SYSTEM_VERILOG_OPERATOR(TOK_LSQASTERIC, "[*"); }
269+
"[+" { SYSTEM_VERILOG_OPERATOR(TOK_LSQPLUS, "[+"); }
270+
"[=" { SYSTEM_VERILOG_OPERATOR(TOK_LSQEQUAL, "[="); }
271+
"[->" { SYSTEM_VERILOG_OPERATOR(TOK_LSQMINUSGREATER, "[->"); }
267272

268273
/* Verilog 1364-1995 keywords */
269274

src/verilog/verilog_typecheck_expr.cpp

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2163,6 +2163,16 @@ exprt verilog_typecheck_exprt::convert_unary_expr(unary_exprt expr)
21632163
throw errort().with_location(expr.source_location())
21642164
<< "no support for 'first_match'";
21652165
}
2166+
else if(expr.id() == ID_sva_sequence_repetition_plus)
2167+
{
2168+
throw errort().with_location(expr.source_location())
2169+
<< "currently no support for [+]";
2170+
}
2171+
else if(expr.id() == ID_sva_sequence_repetition_star)
2172+
{
2173+
throw errort().with_location(expr.source_location())
2174+
<< "currently no support for [*]";
2175+
}
21662176
else if(expr.id() == ID_verilog_explicit_cast)
21672177
{
21682178
// SystemVerilog has got type'(expr). This is an explicit
@@ -2624,6 +2634,21 @@ exprt verilog_typecheck_exprt::convert_binary_expr(binary_exprt expr)
26242634
expr.type() = bool_typet();
26252635
return std::move(expr);
26262636
}
2637+
else if(expr.id() == ID_sva_sequence_non_consecutive_repetition)
2638+
{
2639+
throw errort().with_location(expr.source_location())
2640+
<< "currently no support for [=]";
2641+
}
2642+
else if(expr.id() == ID_sva_sequence_consecutive_repetition)
2643+
{
2644+
throw errort().with_location(expr.source_location())
2645+
<< "currently no support for [*]";
2646+
}
2647+
else if(expr.id() == ID_sva_sequence_goto_repetition)
2648+
{
2649+
throw errort().with_location(expr.source_location())
2650+
<< "currently no support for [->]";
2651+
}
26272652
else
26282653
{
26292654
// type is guessed for now

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