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1 parent cba05a7 commit df88c11Copy full SHA for df88c11
src/lib.rs
@@ -331,9 +331,9 @@ fn build_isa(sess: &Session, backend_config: &BackendConfig) -> Arc<dyn TargetIs
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sess.dcx().fatal(format!("can't compile for {}: {}", target_triple, err));
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});
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if target_triple.architecture == target_lexicon::Architecture::X86_64 {
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- // Don't use "haswell" as the default, as it implies `has_lzcnt`.
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- // macOS CI is still at Ivy Bridge EP, so `lzcnt` is interpreted as `bsr`.
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- builder.enable("nehalem").unwrap();
+ // Only set the target cpu on x86_64 as Cranelift is missing
+ // the target cpu list for most other targets.
+ builder.enable(sess.target.cpu.as_ref()).unwrap();
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}
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builder
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