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Many of our sketches would not load as they did not fit in memory regions - Also enabled DMA based SPI #32

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KurtE
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@KurtE KurtE commented Jan 16, 2025

Edit: This may partially address #15 at least for the short term. Long term hopefully have more control
over this maybe on per sketch basis?

Not sure if this is the best approach, but I know that a lot of sketches that @mjs513 and I have been
experimenting with on Zephyr will not load do to not fitting into memory regions.

So did one commit that increased the size to the size that @mjs513 sent me, and it appears to works with
a lot more sketches.

I also had a second commit where I added two items conf file that enables Asynchronous SPI operations on
the giga.

I reran my simple ILI9341 test sketch which does fill screens of the display using a few methods, including this.

KurtE added 2 commits January 16, 2025 11:52
…ding

I found that the majority of the sketches I would try would not load with the current default
settings.

Not sure how large they need to be, but this has worked for most of my sketches and I believe @mjs513 test sketches as well
These two configuration settings are needed to enable the SPI Async code to work in Zephyr on STM32 based boards.
@mjs513
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mjs513 commented Jan 17, 2025

I agree with @KurtE - with out the changes to the conf file for region sizes most of the sketches I tested would not run.

… for PWM

The code was already there, but  before it checked that the index was valid
it first checked if the pwm was ready,  So moved the check up before that.
@KurtE
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KurtE commented Jan 18, 2025

I pushed up the change that keeps analogWrite from faulting processor, if the passed in pin was not currently defined as
pwm. Code was there to check, but it first checked to see if the pwm pin was in ready state, so moved check up...

Can move this to it's own PR if needed.

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Hi @KurtE ,
I'm going to manually merge the patches and split the last one between code and rebuild 🙂
Thanks!

@facchinm facchinm closed this Jan 22, 2025
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3 participants