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Reducing rr_node and rr_edge count in fpga_interchange node translation step
Combine node forest to single tree Signed-off-by: Maciej Dudek <[email protected]>
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3 files changed

+696
-415
lines changed

3 files changed

+696
-415
lines changed

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 28 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -259,7 +259,6 @@ struct ArchReader {
259259

260260
// Bel Cell mappings
261261
std::unordered_map<uint32_t, std::set<t_bel_cell_mapping>> bel_cell_mappings_;
262-
std::unordered_map<std::string, int> segment_name_to_segment_idx;
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264263
// Utils
265264

@@ -2370,6 +2369,29 @@ struct ArchReader {
23702369
}
23712370
}
23722371

2372+
void add_segment_with_default_values(t_segment_inf& seg, std::string name) {
2373+
// Use default values as we will populate rr_graph with correct values
2374+
// This segments are just declaration of future use
2375+
seg.name = name;
2376+
seg.length = 1;
2377+
seg.frequency = 1;
2378+
seg.Rmetal = 1e-12;
2379+
seg.Cmetal = 1e-12;
2380+
seg.parallel_axis = BOTH_AXIS;
2381+
2382+
// TODO: Only bi-directional segments are created, but it the interchange format
2383+
// has directionality information on PIPs, which may be used to infer the
2384+
// segments' directonality.
2385+
seg.directionality = BI_DIRECTIONAL;
2386+
seg.arch_wire_switch = 1;
2387+
seg.arch_opin_switch = 1;
2388+
seg.cb.resize(1);
2389+
seg.cb[0] = true;
2390+
seg.sb.resize(2);
2391+
seg.sb[0] = true;
2392+
seg.sb[1] = true;
2393+
}
2394+
23732395
void process_segments() {
23742396
// Segment names will be taken from wires connected to pips
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// They are good representation for nodes
@@ -2382,32 +2404,14 @@ struct ArchReader {
23822404
}
23832405
}
23842406

2385-
int num_seg = wire_names.size();
2407+
int num_seg = wire_names.size() + 1;
23862408

23872409
arch_->Segments.resize(num_seg);
2388-
size_t index = 0;
2410+
2411+
size_t index = 1;
2412+
add_segment_with_default_values(arch_->Segments[0], std::string("__generic__"));
23892413
for (auto i : wire_names) {
2390-
// Use default values as we will populate rr_graph with correct values
2391-
// This segments are just declaration of future use
2392-
arch_->Segments[index].name = str(i);
2393-
arch_->Segments[index].length = 1;
2394-
arch_->Segments[index].frequency = 1;
2395-
arch_->Segments[index].Rmetal = 1e-12;
2396-
arch_->Segments[index].Cmetal = 1e-12;
2397-
arch_->Segments[index].parallel_axis = BOTH_AXIS;
2398-
2399-
// TODO: Only bi-directional segments are created, but it the interchange format
2400-
// has directionality information on PIPs, which may be used to infer the
2401-
// segments' directonality.
2402-
arch_->Segments[index].directionality = BI_DIRECTIONAL;
2403-
arch_->Segments[index].arch_wire_switch = 1;
2404-
arch_->Segments[index].arch_opin_switch = 1;
2405-
arch_->Segments[index].cb.resize(1);
2406-
arch_->Segments[index].cb[0] = true;
2407-
arch_->Segments[index].sb.resize(2);
2408-
arch_->Segments[index].sb[0] = true;
2409-
arch_->Segments[index].sb[1] = true;
2410-
segment_name_to_segment_idx[str(i)] = index;
2414+
add_segment_with_default_values(arch_->Segments[index], str(i));
24112415
++index;
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}
24132417
}

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