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Reducing rr_node and rr_edge count in fpga_interchange node translation step
Combine node forest to single tree Signed-off-by: Maciej Dudek <[email protected]>
1 parent e52b51b commit 4bafbc5

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3 files changed

+696
-415
lines changed

3 files changed

+696
-415
lines changed

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 28 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -259,7 +259,6 @@ struct ArchReader {
259259

260260
// Bel Cell mappings
261261
std::unordered_map<uint32_t, std::set<t_bel_cell_mapping>> bel_cell_mappings_;
262-
std::unordered_map<std::string, int> segment_name_to_segment_idx;
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264263
// Utils
265264

@@ -2327,6 +2326,29 @@ struct ArchReader {
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}
23282327
}
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2329+
void add_segment_with_default_values(t_segment_inf& seg, std::string name) {
2330+
// Use default values as we will populate rr_graph with correct values
2331+
// This segments are just declaration of future use
2332+
seg.name = name;
2333+
seg.length = 1;
2334+
seg.frequency = 1;
2335+
seg.Rmetal = 1e-12;
2336+
seg.Cmetal = 1e-12;
2337+
seg.parallel_axis = BOTH_AXIS;
2338+
2339+
// TODO: Only bi-directional segments are created, but it the interchange format
2340+
// has directionality information on PIPs, which may be used to infer the
2341+
// segments' directonality.
2342+
seg.directionality = BI_DIRECTIONAL;
2343+
seg.arch_wire_switch = 1;
2344+
seg.arch_opin_switch = 1;
2345+
seg.cb.resize(1);
2346+
seg.cb[0] = true;
2347+
seg.sb.resize(2);
2348+
seg.sb[0] = true;
2349+
seg.sb[1] = true;
2350+
}
2351+
23302352
void process_segments() {
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// Segment names will be taken from wires connected to pips
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// They are good representation for nodes
@@ -2339,32 +2361,14 @@ struct ArchReader {
23392361
}
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}
23412363

2342-
int num_seg = wire_names.size();
2364+
int num_seg = wire_names.size() + 1;
23432365

23442366
arch_->Segments.resize(num_seg);
2345-
size_t index = 0;
2367+
2368+
size_t index = 1;
2369+
add_segment_with_default_values(arch_->Segments[0], std::string("__generic__"));
23462370
for (auto i : wire_names) {
2347-
// Use default values as we will populate rr_graph with correct values
2348-
// This segments are just declaration of future use
2349-
arch_->Segments[index].name = str(i);
2350-
arch_->Segments[index].length = 1;
2351-
arch_->Segments[index].frequency = 1;
2352-
arch_->Segments[index].Rmetal = 1e-12;
2353-
arch_->Segments[index].Cmetal = 1e-12;
2354-
arch_->Segments[index].parallel_axis = BOTH_AXIS;
2355-
2356-
// TODO: Only bi-directional segments are created, but it the interchange format
2357-
// has directionality information on PIPs, which may be used to infer the
2358-
// segments' directonality.
2359-
arch_->Segments[index].directionality = BI_DIRECTIONAL;
2360-
arch_->Segments[index].arch_wire_switch = 1;
2361-
arch_->Segments[index].arch_opin_switch = 1;
2362-
arch_->Segments[index].cb.resize(1);
2363-
arch_->Segments[index].cb[0] = true;
2364-
arch_->Segments[index].sb.resize(2);
2365-
arch_->Segments[index].sb[0] = true;
2366-
arch_->Segments[index].sb[1] = true;
2367-
segment_name_to_segment_idx[str(i)] = index;
2371+
add_segment_with_default_values(arch_->Segments[index], str(i));
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++index;
23692373
}
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}

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