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Code formatting
Signed-off-by: Maciej Kurc <[email protected]>
1 parent 22c1598 commit 2f18d00

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2 files changed

+42
-65
lines changed

2 files changed

+42
-65
lines changed

‎vpr/src/base/write_interchange_netlist.cpp

Lines changed: 40 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -13,23 +13,19 @@
1313

1414
#include <zlib.h>
1515

16-
1716
// ============================================================================
1817

19-
2018
class NetlistBuilder {
21-
public:
22-
19+
public:
2320
using Direction = ::LogicalNetlist::Netlist::Direction;
2421

2522
// ....................................................
2623

27-
NetlistBuilder (const AtomNetlist& netlist, const t_arch& arch) :
28-
netlist_(netlist),
29-
arch_(arch)
30-
{}
24+
NetlistBuilder(const AtomNetlist& netlist, const t_arch& arch)
25+
: netlist_(netlist)
26+
, arch_(arch) {}
3127

32-
void build (LogicalNetlist::Netlist::Builder& logical_netlist) {
28+
void build(LogicalNetlist::Netlist::Builder& logical_netlist) {
3329
logical_netlist.setName(netlist_.netlist_name());
3430

3531
// Build and serialize cell library
@@ -47,8 +43,7 @@ class NetlistBuilder {
4743

4844
// ....................................................
4945

50-
protected:
51-
46+
protected:
5247
typedef std::unordered_map<std::string, std::string> Properties;
5348

5449
struct Port {
@@ -103,8 +98,7 @@ class NetlistBuilder {
10398

10499
// ....................................................
105100

106-
void buildLibrary (LogicalNetlist::Netlist::Builder& logical_netlist) {
107-
101+
void buildLibrary(LogicalNetlist::Netlist::Builder& logical_netlist) {
108102
// Collect models and their ports
109103
std::unordered_map<std::string, const t_model*> models;
110104
for (const auto blk : netlist_.blocks()) {
@@ -147,7 +141,7 @@ class NetlistBuilder {
147141
cellDecls[decl.index].setView(strId("netlist"));
148142
cellDecls[decl.index].setLib(strId("work"));
149143
auto ports = cellDecls[decl.index].initPorts(decl.ports.size());
150-
for (size_t i=0; i<decl.ports.size(); ++i) {
144+
for (size_t i = 0; i < decl.ports.size(); ++i) {
151145
const auto& port = ports_.at(std::make_pair(it.first, decl.ports[i]));
152146
ports.set(i, port.index);
153147
}
@@ -157,8 +151,7 @@ class NetlistBuilder {
157151
}
158152
}
159153

160-
void buildNetlist (LogicalNetlist::Netlist::Builder& logical_netlist) {
161-
154+
void buildNetlist(LogicalNetlist::Netlist::Builder& logical_netlist) {
162155
// Add cell instances
163156
for (const auto blk : netlist_.blocks()) {
164157
const t_model* model = netlist_.block_model(blk);
@@ -230,22 +223,21 @@ class NetlistBuilder {
230223
auto cellList = logical_netlist.initCellList(groups.size());
231224
size_t groupIndex = 0;
232225
for (const auto& it : groups) {
233-
const auto type = it.first;
226+
const auto type = it.first;
234227
const auto& group = it.second;
235228

236229
cellList[groupIndex].setIndex(cellDeclarations_.at(type).index);
237230

238231
// Instances
239232
auto insts = cellList[groupIndex].initInsts(group.instances.size());
240-
for (size_t i=0; i<group.instances.size(); ++i) {
233+
for (size_t i = 0; i < group.instances.size(); ++i) {
241234
insts.set(i, group.instances[i]);
242235
}
243236

244237
// Nets
245238
auto nets = cellList[groupIndex].initNets(group.nets.size());
246239
size_t netIndex = 0;
247240
for (const auto& net_name : group.nets) {
248-
249241
VTR_ASSERT(nets_.find(net_name) != nets_.end());
250242
const auto& net = nets_.at(net_name);
251243

@@ -264,10 +256,8 @@ class NetlistBuilder {
264256

265257
// Serialize
266258
auto portInsts = nets[netIndex].initPortInsts(ports.size());
267-
for (size_t i=0; i<ports.size(); ++i) {
268-
269-
auto key = ports[i].isTop ? std::make_pair(netlist_.netlist_name(), net_name) :
270-
std::make_pair(type, ports[i].port);
259+
for (size_t i = 0; i < ports.size(); ++i) {
260+
auto key = ports[i].isTop ? std::make_pair(netlist_.netlist_name(), net_name) : std::make_pair(type, ports[i].port);
271261

272262
const auto& port = ports_.at(key);
273263
portInsts[i].setPort(port.index);
@@ -297,7 +287,7 @@ class NetlistBuilder {
297287
}
298288
}
299289

300-
void buildPropertyMap (::LogicalNetlist::Netlist::PropertyMap::Builder& propertyMap, const Properties& properties) {
290+
void buildPropertyMap(::LogicalNetlist::Netlist::PropertyMap::Builder& propertyMap, const Properties& properties) {
301291
auto entries = propertyMap.initEntries(properties.size());
302292
size_t index = 0;
303293

@@ -310,12 +300,11 @@ class NetlistBuilder {
310300

311301
// ....................................................
312302

313-
static bool isIoModel (const char* str) {
314-
return !strcmp(str, MODEL_INPUT) ||
315-
!strcmp(str, MODEL_OUTPUT);
303+
static bool isIoModel(const char* str) {
304+
return !strcmp(str, MODEL_INPUT) || !strcmp(str, MODEL_OUTPUT);
316305
}
317306

318-
uint32_t strId (const std::string& str) {
307+
uint32_t strId(const std::string& str) {
319308
if (strings_.count(str)) {
320309
return strings_[str];
321310
} else {
@@ -325,8 +314,7 @@ class NetlistBuilder {
325314
}
326315
}
327316

328-
void addCellDeclaration (const t_model* model) {
329-
317+
void addCellDeclaration(const t_model* model) {
330318
// Already exists
331319
auto it = cellDeclarations_.find(model->name);
332320
if (it != cellDeclarations_.end()) {
@@ -337,11 +325,11 @@ class NetlistBuilder {
337325
CellDeclaration decl;
338326

339327
// Collect ports
340-
for(t_model_ports* p=model->inputs; p; p=p->next) {
328+
for (t_model_ports* p = model->inputs; p; p = p->next) {
341329
addPort(model->name, p, Direction::INPUT);
342330
decl.ports.push_back(p->name);
343331
}
344-
for(t_model_ports* p=model->outputs; p; p=p->next) {
332+
for (t_model_ports* p = model->outputs; p; p = p->next) {
345333
addPort(model->name, p, Direction::OUTPUT);
346334
decl.ports.push_back(p->name);
347335
}
@@ -358,8 +346,7 @@ class NetlistBuilder {
358346
cellDeclarations_.emplace(std::make_pair(model->name, decl));
359347
}
360348

361-
void addPort (const std::string& modelName, const t_model_ports* modelPort, Direction dir) {
362-
349+
void addPort(const std::string& modelName, const t_model_ports* modelPort, Direction dir) {
363350
// Already exists
364351
auto it = ports_.find(std::make_pair(modelName, modelPort->name));
365352
if (it != ports_.end()) {
@@ -369,7 +356,7 @@ class NetlistBuilder {
369356
// Build the port
370357
Port port;
371358
port.dir = dir;
372-
359+
373360
if (modelPort->size > 1) {
374361
port.isBus = true;
375362
port.bitLo = 0;
@@ -390,12 +377,12 @@ class NetlistBuilder {
390377
port.properties["is_non_clock_global"] = "1";
391378
}
392379

393-
// Add the port
380+
// Add the port
394381
port.index = ports_.size();
395382
ports_.emplace(std::make_pair(std::make_pair(modelName, modelPort->name), port));
396383
};
397384

398-
uint32_t addCellInstance (const AtomBlockId& block) {
385+
uint32_t addCellInstance(const AtomBlockId& block) {
399386
const t_model* model = netlist_.block_model(block);
400387
VTR_ASSERT(model != nullptr);
401388

@@ -408,7 +395,7 @@ class NetlistBuilder {
408395
auto addProperty = [&](const std::pair<std::string, std::string>& prop) {
409396
if (inst.properties.count(prop.first)) {
410397
VTR_LOG_WARN("Duplicate property '%s'='%s' of cell instance '%s'\n",
411-
prop.first.c_str(), prop.second.c_str(), inst.name.c_str());
398+
prop.first.c_str(), prop.second.c_str(), inst.name.c_str());
412399
} else {
413400
inst.properties.insert(prop);
414401
}
@@ -431,30 +418,28 @@ class NetlistBuilder {
431418
return inst.index;
432419
}
433420

434-
void addNet (const AtomNetId& net_id) {
435-
421+
void addNet(const AtomNetId& net_id) {
436422
Net net;
437423

438424
// Handle driver / endpoints
439425
for (const auto& pin_id : netlist_.net_pins(net_id)) {
440-
441426
// Block
442-
const auto& blk_id = netlist_.pin_block(pin_id);
443-
const auto& blk_name = netlist_.block_name(blk_id);
427+
const auto& blk_id = netlist_.pin_block(pin_id);
428+
const auto& blk_name = netlist_.block_name(blk_id);
444429

445430
// Port / bit
446-
const auto& port_id = netlist_.pin_port(pin_id);
447-
const auto& port_bit = netlist_.pin_port_bit(pin_id);
431+
const auto& port_id = netlist_.pin_port(pin_id);
432+
const auto& port_bit = netlist_.pin_port_bit(pin_id);
448433
const auto& port_name = netlist_.port_name(port_id);
449434

450435
// Find the cell declaration
451436
const t_model* model = netlist_.block_model(blk_id);
452437
VTR_ASSERT(model != nullptr);
453438

454-
PortInstance portInst;
455-
portInst.cell = blk_name;
456-
portInst.port = port_name;
457-
portInst.bit = port_bit;
439+
PortInstance portInst;
440+
portInst.cell = blk_name;
441+
portInst.port = port_name;
442+
portInst.bit = port_bit;
458443
portInst.isTop = isIoModel(model->name);
459444

460445
net.ports[model->name].push_back(portInst);
@@ -466,8 +451,7 @@ class NetlistBuilder {
466451
nets_.emplace(std::make_pair(name, net));
467452
}
468453

469-
uint32_t buildTopLevelCellDeclaration () {
470-
454+
uint32_t buildTopLevelCellDeclaration() {
471455
CellDeclaration decl;
472456

473457
// Collect top-level ports
@@ -486,12 +470,10 @@ class NetlistBuilder {
486470
if (!strcmp(model->name, MODEL_INPUT)) {
487471
VTR_ASSERT(netlist_.block_output_pins(blk_id).size() == 1);
488472
port.dir = Direction::INPUT;
489-
}
490-
else if (!strcmp(model->name, MODEL_OUTPUT)) {
473+
} else if (!strcmp(model->name, MODEL_OUTPUT)) {
491474
VTR_ASSERT(netlist_.block_input_pins(blk_id).size() == 1);
492475
port.dir = Direction::OUTPUT;
493-
}
494-
else {
476+
} else {
495477
VTR_ASSERT(false);
496478
}
497479

@@ -524,16 +506,13 @@ class NetlistBuilder {
524506

525507
// ============================================================================
526508

527-
528-
void write_interchange_netlist (
509+
void write_interchange_netlist(
529510
const std::string& ic_netlist_file,
530511
const AtomNetlist& netlist,
531-
const t_arch& arch)
532-
{
512+
const t_arch& arch) {
533513
// Initialize the builder
534514
::capnp::MallocMessageBuilder message;
535-
LogicalNetlist::Netlist::Builder logical_netlist =
536-
message.initRoot<LogicalNetlist::Netlist>();
515+
LogicalNetlist::Netlist::Builder logical_netlist = message.initRoot<LogicalNetlist::Netlist>();
537516

538517
// Build the netlist
539518
auto builder = NetlistBuilder(netlist, arch);

‎vpr/src/base/write_interchange_netlist.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,9 @@
55
#include "atom_netlist_fwd.h"
66
#include "vpr_types.h"
77

8-
void write_interchange_netlist (
8+
void write_interchange_netlist(
99
const std::string& ic_netlist_file,
1010
const AtomNetlist& netlist,
11-
const t_arch& arch
12-
);
11+
const t_arch& arch);
1312

1413
#endif /*WRITE_INTERCHANGE_NETLIST_H*/
15-

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