Added reading LUT elements from FPGA interchange

Signed-off-by: Maciej Kurc <[email protected]>

Author: mkurc-ant

libs/libarchfpga/src/physical_types.h

@@ -1743,6 +1743,24 @@ struct t_lut_bel {
 
     std::vector<std::string> input_pins;
     std::string output_pin;
+
+    bool operator == (const t_lut_bel& other) const {
+        return  name == other.name &&
+                input_pins == other.input_pins &&
+                output_pin == other.output_pin;
+    }
+};
+
+struct t_lut_element {
+    std::string site_type;
+    int width;
+    std::vector<t_lut_bel> lut_bels;
+
+    bool operator == (const t_lut_element& other) const {
+        return  site_type == other.site_type &&
+                width == other.width &&
+                lut_bels == other.lut_bels;
+    }
 };
 
 /*   Detailed routing architecture */
@@ -1780,7 +1798,7 @@ struct t_arch {
 
     // Luts
     std::vector<t_lut_cell> lut_cells;
-    std::vector<t_lut_bel> lut_bels;
+    std::vector<t_lut_element> lut_elements;
 
     //The name of the switch used for the input connection block (i.e. to
     //connect routing tracks to block pins).

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -290,9 +290,12 @@ struct ArchReader {
             if (cell.name == name)
                 return true;
 
-        for (auto bel : arch_->lut_bels)
-            if (bel.name == name)
-                return true;
+        for (const auto& lut_element : arch_->lut_elements) {
+            for (const auto& lut_bel : lut_element.lut_bels) {
+                if (lut_bel.name == name)
+                    return true;
+            }
+        }
 
         return false;
     }
@@ -454,27 +457,26 @@ struct ArchReader {
 
         for (auto lut_elem : lut_def.getLutElements()) {
             for (auto lut : lut_elem.getLuts()) {
-                for (auto bel : lut.getBels()) {
-                    t_lut_bel lut_bel;
-
-                    std::string name = bel.getName().cStr();
-                    lut_bel.name = name;
 
-                    // Check for duplicates
-                    auto is_duplicate = [name](t_lut_bel l) { return l.name == name; };
-                    auto res = std::find_if(arch_->lut_bels.begin(), arch_->lut_bels.end(), is_duplicate);
-                    if (res != arch_->lut_bels.end())
-                        continue;
+                t_lut_element element;
+                element.site_type = lut_elem.getSite().cStr();
+                element.width     = lut.getWidth();
 
+                for (auto bel : lut.getBels()) {
+                    t_lut_bel lut_bel;
+                    lut_bel.name = bel.getName().cStr();
                     std::vector<std::string> ipins;
+
                     for (auto pin : bel.getInputPins())
                         ipins.push_back(pin.cStr());
 
                     lut_bel.input_pins = ipins;
                     lut_bel.output_pin = bel.getOutputPin().cStr();
 
-                    arch_->lut_bels.push_back(lut_bel);
+                    element.lut_bels.push_back(lut_bel);
                 }
+
+                arch_->lut_elements.push_back(element);
             }
         }
     }
@@ -737,10 +739,17 @@ struct ArchReader {
 
         // Check for duplicates
         std::string lut_name = lut->name;
+        t_lut_bel* lut_bel = nullptr;
+
         auto find_lut = [lut_name](t_lut_bel l) { return l.name == lut_name; };
-        auto res = std::find_if(arch_->lut_bels.begin(), arch_->lut_bels.end(), find_lut);
-        VTR_ASSERT(res != arch_->lut_bels.end());
-        auto lut_bel = *res;
+        for (auto& lut_element : arch_->lut_elements) {
+            auto res = std::find_if(lut_element.lut_bels.begin(), lut_element.lut_bels.end(), find_lut);
+            if(res != lut_element.lut_bels.end()) {
+                lut_bel = &*res;
+                break;
+            }
+        }
+        VTR_ASSERT(lut_bel != nullptr);
 
         auto mode = &lut->modes[0];
         mode->name = vtr::strdup("lut");
@@ -760,7 +769,7 @@ struct ArchReader {
         new_leaf->blif_model = vtr::strdup(MODEL_NAMES);
         new_leaf->model = get_model(arch_, std::string(MODEL_NAMES));
 
-        auto in_size = lut_bel.input_pins.size();
+        auto in_size = lut_bel->input_pins.size();
         new_leaf->ports[0] = get_generic_port(arch_, new_leaf, IN_PORT, "in", MODEL_NAMES, in_size);
         new_leaf->ports[1] = get_generic_port(arch_, new_leaf, OUT_PORT, "out", MODEL_NAMES);
 
@@ -781,13 +790,13 @@ struct ArchReader {
             std::string output_string;
 
             if (i < num_pins - 1) {
-                istr << lut_bel.input_pins[i];
+                istr << lut_bel->input_pins[i];
                 ostr << "in[" << i << "]";
                 input_string = std::string(lut->name) + std::string(".") + istr.str();
                 output_string = std::string(new_leaf->name) + std::string(".") + ostr.str();
             } else {
                 istr << "out";
-                ostr << lut_bel.output_pin;
+                ostr << lut_bel->output_pin;
                 input_string = std::string(new_leaf->name) + std::string(".") + istr.str();
                 output_string = std::string(lut->name) + std::string(".") + ostr.str();
             }
@@ -1533,10 +1542,10 @@ struct ArchReader {
         //        the RR graph generation is correct.
         //        This can be removed once the RR graph reader from the interchange
         //        device is ready and functional.
-        int num_seg = 1; //wire_names.size();
+        size_t num_seg = 1; //wire_names.size();
 
         arch_->Segments.resize(num_seg);
-        uint32_t index = 0;
+        size_t index = 0;
         for (auto i : wire_names) {
             if (index >= num_seg) break;