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Reducing rr_node and rr_edge count in fpga_interchange node translation step
Combine node forest to single tree Signed-off-by: Maciej Dudek <[email protected]>
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3 files changed

+696
-415
lines changed

3 files changed

+696
-415
lines changed

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 28 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -259,7 +259,6 @@ struct ArchReader {
259259

260260
// Bel Cell mappings
261261
std::unordered_map<uint32_t, std::set<t_bel_cell_mapping>> bel_cell_mappings_;
262-
std::unordered_map<std::string, int> segment_name_to_segment_idx;
263262

264263
// Utils
265264

@@ -2310,6 +2309,29 @@ struct ArchReader {
23102309
}
23112310
}
23122311

2312+
void add_segment_with_default_values(t_segment_inf& seg, std::string name) {
2313+
// Use default values as we will populate rr_graph with correct values
2314+
// This segments are just declaration of future use
2315+
seg.name = name;
2316+
seg.length = 1;
2317+
seg.frequency = 1;
2318+
seg.Rmetal = 1e-12;
2319+
seg.Cmetal = 1e-12;
2320+
seg.parallel_axis = BOTH_AXIS;
2321+
2322+
// TODO: Only bi-directional segments are created, but it the interchange format
2323+
// has directionality information on PIPs, which may be used to infer the
2324+
// segments' directonality.
2325+
seg.directionality = BI_DIRECTIONAL;
2326+
seg.arch_wire_switch = 1;
2327+
seg.arch_opin_switch = 1;
2328+
seg.cb.resize(1);
2329+
seg.cb[0] = true;
2330+
seg.sb.resize(2);
2331+
seg.sb[0] = true;
2332+
seg.sb[1] = true;
2333+
}
2334+
23132335
void process_segments() {
23142336
// Segment names will be taken from wires connected to pips
23152337
// They are good representation for nodes
@@ -2322,32 +2344,14 @@ struct ArchReader {
23222344
}
23232345
}
23242346

2325-
int num_seg = wire_names.size();
2347+
int num_seg = wire_names.size() + 1;
23262348

23272349
arch_->Segments.resize(num_seg);
2328-
size_t index = 0;
2350+
2351+
size_t index = 1;
2352+
add_segment_with_default_values(arch_->Segments[0], std::string("__generic__"));
23292353
for (auto i : wire_names) {
2330-
// Use default values as we will populate rr_graph with correct values
2331-
// This segments are just declaration of future use
2332-
arch_->Segments[index].name = str(i);
2333-
arch_->Segments[index].length = 1;
2334-
arch_->Segments[index].frequency = 1;
2335-
arch_->Segments[index].Rmetal = 1e-12;
2336-
arch_->Segments[index].Cmetal = 1e-12;
2337-
arch_->Segments[index].parallel_axis = BOTH_AXIS;
2338-
2339-
// TODO: Only bi-directional segments are created, but it the interchange format
2340-
// has directionality information on PIPs, which may be used to infer the
2341-
// segments' directonality.
2342-
arch_->Segments[index].directionality = BI_DIRECTIONAL;
2343-
arch_->Segments[index].arch_wire_switch = 1;
2344-
arch_->Segments[index].arch_opin_switch = 1;
2345-
arch_->Segments[index].cb.resize(1);
2346-
arch_->Segments[index].cb[0] = true;
2347-
arch_->Segments[index].sb.resize(2);
2348-
arch_->Segments[index].sb[0] = true;
2349-
arch_->Segments[index].sb[1] = true;
2350-
segment_name_to_segment_idx[str(i)] = index;
2354+
add_segment_with_default_values(arch_->Segments[index], str(i));
23512355
++index;
23522356
}
23532357
}

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