[Flow]: Adding verilog header files to run Koios design with and with…

vtr_flow/benchmarks/verilog/koios/attention_layer_complex_dsp.vh

@@ -0,0 +1,7 @@
+/*
+ * attention_layer design including complex dsp definition
+*/
+
+`define complex_dsp
+
+`include "./generic_circuits/attention_layer.v"

vtr_flow/benchmarks/verilog/koios/conv_layer_complex_dsp.vh

@@ -0,0 +1,28 @@
+/*
+ * conv_layer_hls design including complex dsp definition
+*/
+
+`define complex_dsp
+module dpram ( 
+
+    clk, 
+
+    address_a, 
+
+    address_b, 
+
+    wren_a, 
+
+    wren_b, 
+
+    data_a, 
+
+    data_b, 
+
+    out_a, 
+
+    out_b 
+
+); 
+
+`include "./generic_circuits/conv_layer_hls.v"

vtr_flow/benchmarks/verilog/koios/dla_like.medium_complex_dsp.vh

@@ -0,0 +1,60 @@
+/*
+ * dla_like.medium design including complex dsp definition
+*/
+
+`define complex_dsp
+module DLA (
+	input clk,
+	input i_reset,
+	input [15:0] i_ddr_0_0,
+	output o_dummy_out_0_0,
+	input [15:0] i_ddr_0_1,
+	output o_dummy_out_0_1,
+	input [15:0] i_ddr_0_2,
+	output o_dummy_out_0_2,
+	input [15:0] i_ddr_0_3,
+	output o_dummy_out_0_3,
+	input [15:0] i_ddr_1_0,
+	output o_dummy_out_1_0,
+	input [15:0] i_ddr_1_1,
+	output o_dummy_out_1_1,
+	input [15:0] i_ddr_1_2,
+	output o_dummy_out_1_2,
+	input [15:0] i_ddr_1_3,
+	output o_dummy_out_1_3,
+	input [15:0] i_ddr_2_0,
+	output o_dummy_out_2_0,
+	input [15:0] i_ddr_2_1,
+	output o_dummy_out_2_1,
+	input [15:0] i_ddr_2_2,
+	output o_dummy_out_2_2,
+	input [15:0] i_ddr_2_3,
+	output o_dummy_out_2_3,
+	input [15:0] i_ddr_3_0,
+	output o_dummy_out_3_0,
+	input [15:0] i_ddr_3_1,
+	output o_dummy_out_3_1,
+	input [15:0] i_ddr_3_2,
+	output o_dummy_out_3_2,
+	input [15:0] i_ddr_3_3,
+	output o_dummy_out_3_3,
+	input [15:0] i_ddr_4_0,
+	output o_dummy_out_4_0,
+	input [15:0] i_ddr_4_1,
+	output o_dummy_out_4_1,
+	input [15:0] i_ddr_4_2,
+	output o_dummy_out_4_2,
+	input [15:0] i_ddr_4_3,
+	output o_dummy_out_4_3,
+	input [15:0] i_ddr_5_0,
+	output o_dummy_out_5_0,
+	input [15:0] i_ddr_5_1,
+	output o_dummy_out_5_1,
+	input [15:0] i_ddr_5_2,
+	output o_dummy_out_5_2,
+	input [15:0] i_ddr_5_3,
+	output o_dummy_out_5_3,
+	output o_valid
+);
+
+`include "./generic_circuits/dla_like.medium.v"

vtr_flow/benchmarks/verilog/koios/dla_like.small_complex_dsp.vh

@@ -0,0 +1,36 @@
+/*
+ * dla_like.small design including complex dsp definition
+*/
+
+`define complex_dsp
+module DLA (
+	input clk,
+	input i_reset,
+	input [15:0] i_ddr_0_0,
+	output o_dummy_out_0_0,
+	input [15:0] i_ddr_0_1,
+	output o_dummy_out_0_1,
+	input [15:0] i_ddr_1_0,
+	output o_dummy_out_1_0,
+	input [15:0] i_ddr_1_1,
+	output o_dummy_out_1_1,
+	input [15:0] i_ddr_2_0,
+	output o_dummy_out_2_0,
+	input [15:0] i_ddr_2_1,
+	output o_dummy_out_2_1,
+	input [15:0] i_ddr_3_0,
+	output o_dummy_out_3_0,
+	input [15:0] i_ddr_3_1,
+	output o_dummy_out_3_1,
+	input [15:0] i_ddr_4_0,
+	output o_dummy_out_4_0,
+	input [15:0] i_ddr_4_1,
+	output o_dummy_out_4_1,
+	input [15:0] i_ddr_5_0,
+	output o_dummy_out_5_0,
+	input [15:0] i_ddr_5_1,
+	output o_dummy_out_5_1,
+	output o_valid
+);
+
+`include "./generic_circuits/dla_like.small.v"

vtr_flow/benchmarks/verilog/koios/eltwise_layer_complex_dsp.vh

@@ -0,0 +1,7 @@
+/*
+ * eltwise_layer design including complex dsp definition
+*/
+
+`define complex_dsp
+
+`include "./generic_circuits/eltwise_layer.v"

vtr_flow/benchmarks/verilog/koios/gemm_layer_complex_dsp.vh

@@ -0,0 +1,7 @@
+/*
+ * gemm_layer design including complex dsp definition
+*/
+
+`define complex_dsp
+
+`include "./generic_circuits/gemm_layer.v"

vtr_flow/benchmarks/verilog/koios/attention_layer.v → vtr_flow/benchmarks/verilog/koios/generic_circuits/attention_layer.v

@@ -4,7 +4,6 @@
 
 //`define SIMULATION_MEMORY
 //`define SIMULATION_addfp
-`define complex_dsp
 `define VECTOR_DEPTH 64 //Q,K,V vector size
 `define DATA_WIDTH 16
 `define VECTOR_BITS 1024 // 16 bit each (16x64)

vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v → vtr_flow/benchmarks/verilog/koios/generic_circuits/conv_layer_hls.v

@@ -18,29 +18,6 @@
 // Abridged for VTR by: Daniel Rauch
 //////////////////////////////////////////////////////////////////////////////
 
-`define complex_dsp
-module dpram ( 
-
-    clk, 
-
-    address_a, 
-
-    address_b, 
-
-    wren_a, 
-
-    wren_b, 
-
-    data_a, 
-
-    data_b, 
-
-    out_a, 
-
-    out_b 
-
-); 
-
 parameter AWIDTH=10; 
 
 parameter NUM_WORDS=1024; 

vtr_flow/benchmarks/verilog/koios/dla_like.medium.v → vtr_flow/benchmarks/verilog/koios/generic_circuits/dla_like.medium.v

@@ -15,61 +15,6 @@
 //4. Double-buffering after each layer. 
 ///////////////////////////////////////////////////////////////////////////////
 
-`define complex_dsp
-module DLA (
-	input clk,
-	input i_reset,
-	input [15:0] i_ddr_0_0,
-	output o_dummy_out_0_0,
-	input [15:0] i_ddr_0_1,
-	output o_dummy_out_0_1,
-	input [15:0] i_ddr_0_2,
-	output o_dummy_out_0_2,
-	input [15:0] i_ddr_0_3,
-	output o_dummy_out_0_3,
-	input [15:0] i_ddr_1_0,
-	output o_dummy_out_1_0,
-	input [15:0] i_ddr_1_1,
-	output o_dummy_out_1_1,
-	input [15:0] i_ddr_1_2,
-	output o_dummy_out_1_2,
-	input [15:0] i_ddr_1_3,
-	output o_dummy_out_1_3,
-	input [15:0] i_ddr_2_0,
-	output o_dummy_out_2_0,
-	input [15:0] i_ddr_2_1,
-	output o_dummy_out_2_1,
-	input [15:0] i_ddr_2_2,
-	output o_dummy_out_2_2,
-	input [15:0] i_ddr_2_3,
-	output o_dummy_out_2_3,
-	input [15:0] i_ddr_3_0,
-	output o_dummy_out_3_0,
-	input [15:0] i_ddr_3_1,
-	output o_dummy_out_3_1,
-	input [15:0] i_ddr_3_2,
-	output o_dummy_out_3_2,
-	input [15:0] i_ddr_3_3,
-	output o_dummy_out_3_3,
-	input [15:0] i_ddr_4_0,
-	output o_dummy_out_4_0,
-	input [15:0] i_ddr_4_1,
-	output o_dummy_out_4_1,
-	input [15:0] i_ddr_4_2,
-	output o_dummy_out_4_2,
-	input [15:0] i_ddr_4_3,
-	output o_dummy_out_4_3,
-	input [15:0] i_ddr_5_0,
-	output o_dummy_out_5_0,
-	input [15:0] i_ddr_5_1,
-	output o_dummy_out_5_1,
-	input [15:0] i_ddr_5_2,
-	output o_dummy_out_5_2,
-	input [15:0] i_ddr_5_3,
-	output o_dummy_out_5_3,
-	output o_valid
-);
-
 wire [15:0] f_buffer_pe_0_0;
 wire valid_buff_0_0;
 wire [15:0] f_buffer_pe_0_1;

vtr_flow/benchmarks/verilog/koios/dla_like.small.v → vtr_flow/benchmarks/verilog/koios/generic_circuits/dla_like.small.v

@@ -15,37 +15,6 @@
 //4. Double-buffering after each layer. 
 ///////////////////////////////////////////////////////////////////////////////
 
-`define complex_dsp
-module DLA (
-	input clk,
-	input i_reset,
-	input [15:0] i_ddr_0_0,
-	output o_dummy_out_0_0,
-	input [15:0] i_ddr_0_1,
-	output o_dummy_out_0_1,
-	input [15:0] i_ddr_1_0,
-	output o_dummy_out_1_0,
-	input [15:0] i_ddr_1_1,
-	output o_dummy_out_1_1,
-	input [15:0] i_ddr_2_0,
-	output o_dummy_out_2_0,
-	input [15:0] i_ddr_2_1,
-	output o_dummy_out_2_1,
-	input [15:0] i_ddr_3_0,
-	output o_dummy_out_3_0,
-	input [15:0] i_ddr_3_1,
-	output o_dummy_out_3_1,
-	input [15:0] i_ddr_4_0,
-	output o_dummy_out_4_0,
-	input [15:0] i_ddr_4_1,
-	output o_dummy_out_4_1,
-	input [15:0] i_ddr_5_0,
-	output o_dummy_out_5_0,
-	input [15:0] i_ddr_5_1,
-	output o_dummy_out_5_1,
-	output o_valid
-);
-
 wire [15:0] f_buffer_pe_0_0;
 wire valid_buff_0_0;
 wire [15:0] f_buffer_pe_0_1;

vtr_flow/benchmarks/verilog/koios/eltwise_layer.v → vtr_flow/benchmarks/verilog/koios/generic_circuits/eltwise_layer.v

@@ -56,7 +56,6 @@
 //section by section. The number of rows will be programmed
 //in the "iterations" register in the design.
 
-`define complex_dsp
 `define BFLOAT16 
 
 // IEEE Half Precision => EXPONENT = 5, MANTISSA = 10

vtr_flow/benchmarks/verilog/koios/gemm_layer.v → vtr_flow/benchmarks/verilog/koios/generic_circuits/gemm_layer.v

@@ -19,7 +19,6 @@
 // with a simpler DSP (just a fixed point multiplier) like in the
 // flagship arch timing/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml
 /////////////////////////////////////////////////////////////////////////
-`define complex_dsp
 `define BFLOAT16 
 
 // IEEE Half Precision => EXPONENT = 5, MANTISSA = 10

vtr_flow/benchmarks/verilog/koios/softmax.v → vtr_flow/benchmarks/verilog/koios/generic_circuits/softmax.v

@@ -14,7 +14,6 @@
 //////////////////////////////////////////////////////////////////////////////
 
 //softmax_p8_smem_rfloat16_alut_v512_b2_-0.1_0.1.v
-`define complex_dsp
 `ifndef DEFINES_DONE
 `define DEFINES_DONE
 `define EXPONENT 5

vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small.v → vtr_flow/benchmarks/verilog/koios/generic_circuits/tiny_darknet_like.small.v

@@ -16,18 +16,6 @@
 //////////////////////////////////////////////////////////////////////////////
 
 `timescale 1 ns / 1 ps 
-`define complex_dsp
-module td_fused_top_Block_entry_proc_proc392 (
-        ap_clk,
-        ap_rst,
-        ap_start,
-        ap_done,
-        ap_continue,
-        ap_idle,
-        ap_ready,
-        tmp,
-        ap_return
-);
 
 parameter    ap_ST_fsm_state1 = 1'd1;
 

vtr_flow/benchmarks/verilog/koios/robot_rl_complex_dsp.vh

@@ -0,0 +1,7 @@
+/*
+ * robot_rl design including complex dsp definition
+*/
+
+`define complex_dsp
+
+`include "./generic_circuits/robot_rl.v"

vtr_flow/benchmarks/verilog/koios/softmax_complex_dsp.vh

@@ -0,0 +1,7 @@
+/*
+ * softmax design including complex dsp definition
+*/
+
+`define complex_dsp
+
+`include "./generic_circuits/softmax.v"

vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small_complex_dsp.vh

@@ -0,0 +1,18 @@
+/*
+ * tiny_darknet_like.small design including complex dsp definition
+*/
+
+`define complex_dsp
+module td_fused_top_Block_entry_proc_proc392 (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        tmp,
+        ap_return
+);
+
+`include "./generic_circuits/tiny_darknet_like.small.v"

vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/config/config.txt → vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/DSP_slice_arch/config/config.txt

@@ -10,13 +10,15 @@ circuits_dir=benchmarks/verilog/koios
 archs_dir=arch/COFFE_22nm
 
 # Add circuits to list to sweep
-circuit_list_add=tpu_like.small.v
-circuit_list_add=dla_like.small.v
-circuit_list_add=bnn.v
-circuit_list_add=attention_layer.v
-circuit_list_add=conv_layer_hls.v
-circuit_list_add=conv_layer.v
-circuit_list_add=gemm_layer.v
+circuit_list_add=attention_layer_complex_dsp.vh
+circuit_list_add=conv_layer_complex_dsp.vh
+circuit_list_add=dla_like.medium_complex_dsp.vh
+circuit_list_add=dla_like.small_complex_dsp.vh
+circuit_list_add=eltwise_layer_complex_dsp.vh
+circuit_list_add=gemm_layer_complex_dsp.vh
+circuit_list_add=softmax_complex_dsp.vh
+circuit_list_add=tiny_darknet_like.small_complex_dsp.vh
+
 
 # Add architectures to list to sweep
 arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml