introduce tbuf to RT logic

Author: cpldcpu

10_HDL/dff.vhd

@@ -0,0 +1,83 @@
+--
+-- Minimal 8 Bit CPU
+--
+-- rev 15102001
+--
+-- 01-02/2001 Tim B"oscke
+-- 10   /2001 slight changes for proper simulation.
+--
+-- [email protected]
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+-- use ieee.std_logic_unsigned.all;
+
+entity CPU8BIT2 is
+	port (	
+		datain:	    in	std_logic_vector(7 downto 0);
+		dataout:	out	std_logic_vector(7 downto 0);
+		adress:	out	std_logic_vector(5 downto 0);
+		oe:		out	std_logic;
+		we:		out	std_logic;		-- Asynchronous memory interface
+		rst:	in	std_logic;
+		clk:	in	std_logic);
+end;
+
+architecture CPU_ARCH of CPU8BIT2 is
+	-- signal	akku:	std_logic_vector(8 downto 0);	-- akku(8) is carry !
+	-- signal	adreg:	std_logic_vector(5 downto 0);
+	-- signal 	pc:	std_logic_vector(5 downto 0);
+	-- signal	states:	std_logic_vector(2 downto 0);
+	signal	akku:	unsigned(8 downto 0);	-- akku(8) is carry !
+	signal	adreg:	unsigned(5 downto 0);
+	signal 	pc:		unsigned(5 downto 0);
+	signal	states:	unsigned(2 downto 0);
+begin
+	process(clk,rst)
+	begin
+
+	if rising_edge(clk) then
+
+		if (rst = '0') then 
+			adreg	<= (others => '0');	-- start execution at memory location 0 
+			states	<= "000";
+			akku <= (others => '0');
+			pc   <= (others => '0');
+		else
+			-- PC / Adress path
+			if (states = "000") then 
+				pc	<= adreg + 1; 
+				adreg	<= unsigned(datain(5 downto 0));
+			else	
+				adreg	<= pc;
+			end if;
+
+			-- ALU / Data Path
+			case states is
+				when "010" => akku <= ("0" & akku(7 downto 0)) + ("0" & unsigned(datain)); 	-- add
+				when "011" => akku(7 downto 0) <= akku(7 downto 0) nor unsigned(datain);	-- nor
+				when "101" => akku(8) <= '0';					-- branch not taken, clear carry
+				when others => null;						-- instr. fetch, jcc taken (000), sta (001) 
+			end case;						
+
+			-- State machine
+			if (states /= "000") then states <= "000"; 				-- fetch next opcode
+			elsif (datain(7 downto 6) = "11" and akku(8)='1') then states <= "101";	-- branch not taken
+				else  states <= "0" & not unsigned(datain(7 downto 6)); 			-- execute instruction	
+			end if;	
+		end if;
+	end if;
+	end process;
+	
+	-- output
+	adress	<= std_logic_vector(adreg);
+--	data 	<= "ZZZZZZZZ" when states /= "001" else std_logic_vector(akku(7 downto 0));
+	dataout	<= "11111111" when states /= "001" else std_logic_vector(akku(7 downto 0));
+	-- dataout	<= std_logic_vector(akku(7 downto 0));
+	oe <= '1' when (clk='1' or states  = "001" or rst='0' or states = "101") else '0'; 	-- no memory access during reset and 
+	we <= '1' when (clk='1' or states /= "001" or rst='0') else '0'; 			-- state "101" (branch not taken)
+	
+end CPU_ARCH;
+	

10_HDL/dice555.vhd

@@ -10,13 +10,18 @@ output Y;
 assign Y = A;
 endmodule
 
+module rt_TBUF_N(A, nE, Y);
+input A, nE;
+output Y;
+assign Y = nE ? 1'bZ : A ;
+endmodule
+
 module rt_NOT(A, Y);
 input A;
 output Y;
 assign Y = ~A;
 endmodule
 
-
 module rt_XOR2(A, B, Y);
 input A, B;
 output Y;

10_HDL/mcpu_sepdata.vhd

@@ -20,7 +20,16 @@ library(SingleLogicCells) {
     pin(Y) { direction: output;
               function: "A"; }
   }
-  
+
+  cell(rt_TBUF_N) {
+    area: 3;
+    pin(A) { direction: input; }
+    pin(nE) { direction: input; }
+    pin(Y) { direction: output;
+        function : "A";
+        three_state : "~nE"; }
+  }
+
   cell(rt_NOT) {
     area: 1;
     pin(A) { direction: input; }

20_SYNTH/discrete_RT_logic_cells.v

@@ -27,9 +27,9 @@ LATCH_N _TECHMAP_REPLACE_ (
 endmodule
 
 module \$_TBUF_ (input A, input E, output Y);
-TBUF _TECHMAP_REPLACE_ (
+rt_TBUF_N _TECHMAP_REPLACE_ (
 .A(A),
-.E(E),
+.E(!E),
 .Y(Y)
 );
 endmodule

20_SYNTH/discrete_RT_logic_liberty.lib

@@ -21,6 +21,7 @@ tribuf
 
 # Technology mapping
 techmap
+techmap -map ../20_SYNTH/discrete_RT_techmap.v   # map TBUF
 
 # Work around to map DFF with sync set/reset, since this is not possible in liberty file
 # proc; opt;

20_SYNTH/discrete_RT_techmap.v

@@ -602,9 +602,12 @@ def addlogiccell(self,name,celltype, nets):
             self.insertcell(name+"a","rt_NOT", [nets[0], nets[3]])
             self.insertcell(name+"b","rt_NOT", [nets[1], nets[3]])
             self.insertcell(name+"c","rt_NOT", [nets[2], nets[3]])
+        elif celltype == "rt_TBUF_N":
+            self.addlogiccell(name+"a","rt_NOR2", [nets[0] , nets[1], name+"a"])
+            self.addlogiccell(name+"b","rt_NOT" , [name+"a", nets[2] ])
         elif celltype == "rt_DFF":  # pin order: C, D, Q
-            self.insertcell(name+"c#","rt_NOT", [nets[0]  , name+"CI"] )   # clock inversion
-            self.insertcell(name+"d","rt_NOT", [name+"CI", name+"CNI"])   # clock inversion
+            self.insertcell(name+"c#","rt_NOT", [nets[0]  , name+"CI" ])   # clock inversion
+            self.insertcell(name+"d" ,"rt_NOT", [name+"CI", name+"CNI"])   # clock inversion
             self.addlogiccell(name+"a","PHLATCH", [name+"CI" , nets[1]  , name+"DI"])  # pin order: E, D, Q
             self.addlogiccell(name+"b","PHLATCH", [name+"CNI", name+"DI", nets[2]  ])  # pin order: E, D, Q
         elif celltype == "PHLATCH":  # pin order: E, D, Q
@@ -1129,8 +1132,8 @@ def detailedoptimization(startarray, initialtemp=1, coolingrate=0.95, optimizati
 
 # !!! You need to update the lines below to adjust for your design!!! 
 
-ArrayXwidth = 7        # This is the width of the grid and should be equal to or larger than the number of I/O pins plus two supply pins!
-DesignArea  = 70        # This is the number of unit cells required for the design. It is outputted as "chip area" during the Synthesis step
+ArrayXwidth = 28        # This is the width of the grid and should be equal to or larger than the number of I/O pins plus two supply pins!
+DesignArea  = 720        # This is the number of unit cells required for the design. It is outputted as "chip area" during the Synthesis step
                         # Fixedio fixes I/O positions within the first row. Leave empty if you want the tool to assign positions.
 FixedIO     = []        # Default, tool assigns I/O
 # FixedIO     =      ["VCC","inv_a", "inv_y", "xor_a", "xor_b", "xor_y", "and_a", "and_b", "and_y", "d", "clk", "q"] # for moregates.vhd
@@ -1146,7 +1149,7 @@ def detailedoptimization(startarray, initialtemp=1, coolingrate=0.95, optimizati
 
 # Optimizer settings. Only change when needed
 
-AreaMargin = 0.5       # This is additional area that is reserved for empty cells. This value should be larger than zero to allow optimization.
+AreaMargin = 0.2       # This is additional area that is reserved for empty cells. This value should be larger than zero to allow optimization.
                         # Too large values will result in waste of area. Default: 0.3
 CoarseAttempts = 20     # Default: 20
 CoarseCycles   = 1000   # Default: 1000
@@ -1165,12 +1168,12 @@ def detailedoptimization(startarray, initialtemp=1, coolingrate=0.95, optimizati
 
 # File names. Don't touch unless you want to modify the flow
 
-InputFileName = "209_synthesized_output.sp"
-PCBTemplateFile = "../30_PLACE/board_template.brd" 
-PCBOutputFile = "309_board_output.brd"
-SpiceOutputFile = "308_extracted_netlist.sp"
-FanoutOutputFile = "307_fanout.txt"
-NetsOutputFile  = "306_nets.csv"
+InputFileName       = "209_synthesized_output.sp"
+PCBTemplateFile     = "../30_PLACE/board_template.brd" 
+PCBOutputFile       = "309_board_output.brd"
+SpiceOutputFile     = "308_extracted_netlist.sp"
+FanoutOutputFile    = "307_fanout.txt"
+NetsOutputFile      = "306_nets.csv"
 PlacementOutputFile = "305_placement.csv"
 
 # =========== START OF MAIN ===============================