Merge pull request #21 from jposada202020/changing_assertions

removing assert statements

Author: jposada202020

adafruit_si5351.py

@@ -169,10 +169,11 @@ def _configure_registers(self, p1, p2, p3):
             self._si5351._write_u8(_SI5351_REGISTER_177_PLL_RESET, (1 << 7) | (1 << 5))
 
         def configure_integer(self, multiplier):
-            """Configure the PLL with a simple integer mulitplier for the most
+            """Configure the PLL with a simple integer multiplier for the most
             accurate (but more limited) PLL frequency generation.
             """
-            assert 14 < multiplier < 91
+            if multiplier >= 91 or multiplier <= 14:
+                raise Exception("Multiplier must be in range 14 to 91.")
             multiplier = int(multiplier)
             # Compute register values and configure them.
             p1 = 128 * multiplier - 512
@@ -192,9 +193,14 @@ def configure_fractional(self, multiplier, numerator, denominator):
             multiplier and numerator/denominator.  This is less accurate and
             susceptible to jitter but allows a larger range of PLL frequencies.
             """
-            assert 14 < multiplier < 91
-            assert 0 < denominator <= 0xFFFFF  # Prevent divide by zero.
-            assert 0 <= numerator < 0xFFFFF
+            if multiplier >= 91 or multiplier <= 14:
+                raise Exception("Multiplier must be in range 14 to 91.")
+            if denominator > 0xFFFFF or denominator <= 0:  # Prevent divide by zero.
+                raise Exception(
+                    "Denominator must be greater than 0 and less than 0xFFFFF."
+                )
+            if numerator >= 0xFFFFF or numerator < 0:
+                raise Exception("Numerator must be in range 0 to 0xFFFFF.")
             multiplier = int(multiplier)
             numerator = int(numerator)
             denominator = int(denominator)
@@ -279,7 +285,8 @@ def r_divider(self):
 
         @r_divider.setter
         def r_divider(self, divider):
-            assert 0 <= divider <= 7
+            if divider > 7 or divider < 0:
+                raise Exception("Divider must in range 0 to 7.")
             reg_value = self._si5351._read_u8(self._r)
             reg_value &= 0x0F
             divider &= 0x07
@@ -306,10 +313,12 @@ def configure_integer(self, pll, divider):
             divider.  This is the most accurate way to set the clock output
             frequency but supports less of a range of values.
             """
-            assert 3 < divider < 2049
+            if divider >= 2049 or divider <= 3:
+                raise Exception("Divider must be in range 3 to 2049.")
             divider = int(divider)
             # Make sure the PLL is configured (has a frequency set).
-            assert pll.frequency is not None
+            if pll.frequency is None:
+                raise Exception("PLL must be configured.")
             # Compute MSx register values.
             p1 = 128 * divider - 512
             p2 = 0
@@ -331,14 +340,20 @@ def configure_fractional(self, pll, divider, numerator, denominator):
             fractional divider with numerator/denominator.  Again this is less
             accurate but has a wider range of output frequencies.
             """
-            assert 3 < divider < 2049
-            assert 0 < denominator <= 0xFFFFF  # Prevent divide by zero.
-            assert 0 <= numerator < 0xFFFFF
+            if divider >= 2049 or divider <= 3:
+                raise Exception("Divider must be in range 3 to 2049.")
+            if denominator > 0xFFFFF or denominator <= 0:  # Prevent divide by zero.
+                raise Exception(
+                    "Denominator must be greater than 0 and less than 0xFFFFF."
+                )
+            if numerator >= 0xFFFFF or numerator < 0:
+                raise Exception("Numerator must be in range 0 to 0xFFFFF.")
             divider = int(divider)
             numerator = int(numerator)
             denominator = int(denominator)
             # Make sure the PLL is configured (has a frequency set).
-            assert pll.frequency is not None
+            if pll.frequency is None:
+                raise Exception("PLL must be configured.")
             # Compute MSx register values.
             p1 = int(128 * divider + math.floor(128 * (numerator / denominator)) - 512)
             p2 = int(