Fast channel reads via caching last channel

[caternuson]

A different approach for #27 as suggested by @ladyada here:
#32 (comment)

[ladyada]

question: why ever update the register pointer?

[caternuson]

It is required for every write operation. For reads, it is only need if you want to read a different register.

There is only one conversion result register. So reading the result from a different channel requires doing a write to the config register to change the mux. That's why this fast read is pretty much limited to a single channel. Otherwise the I2C overhead to change the mux slows it way down.

[ladyada]

okidoke!

[caternuson]

OK, this approach then, that's cool. But I think I might need to tweak this again a little. Sry. Realized this yesterday but was AFK. Repeated reads in SINGLE SHOT will still require writing to the config register to actually start the conversion - gotta set the OS bit. So just need to tweak the logic a little.

[ladyada]

np thank you for the perseverence
!

[caternuson]

Hmmm. Should I just make a second PR for the updates. Or is there a fancier way to revert this merge and then re-merge with the updates?