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K48, K52, K76 boards support added
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‎README.md

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@@ -19,9 +19,15 @@ ArduinoCore-stm32l0 is targeted at ultra low power scenarios, sensor hubs, with
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* [NUCLEO-L053R8](http://www.st.com/en/evaluation-tools/nucleo-l053r8.html)
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* [NUCLEO-L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html)
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### LilyGo
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* [TTGO T-Impulse Wristband](https://github.com/Xinyuan-LilyGO/LilyGo-T-Impulse)
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* [TTGO T-Motion S76G](https://github.com/Xinyuan-LilyGO/LilyGO-T-Motion)
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### AI Thinker / RuiXingHengFang / RisingHF
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* [RHF76-052](http://www.risinghf.com/#/product-details?product_id=5&lang=en)
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### Dragino
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* [LGT92](https://www.dragino.com/products/lora-lorawan-end-node/item/142-lgt-92.html)
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## Installing
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‎boards.txt

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‎variants/K48-S76G-I2C/linker_scripts/STM32L073RZ_FLASH.ld

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/*
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* Copyright (c) 2008-2018 Thomas Roell. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal with the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimers.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimers in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Thomas Roell, nor the names of its contributors
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* may be used to endorse or promote products derived from this Software
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* without specific prior written permission.
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*
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* THE SOFTWARE IS PROVINCED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* WITH THE SOFTWARE.
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*/
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __copy_table_start__
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* __copy_table_end__
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* __zero_table_start__
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* __zero_table_end__
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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* __FlashBase
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* __FlashLimit
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*
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* STM32L0 likes to see .text/.data to be 64 byte aligned.
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*/
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x00030000
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SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00005000
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}
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.text : ALIGN(64)
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{
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KEEP(*(.isr_vector));
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*(.text .text.* .gnu.linkonce.t.*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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*(.rodata .rodata.* .gnu.linkonce.r.*)
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KEEP(*(.eh_frame*))
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (LOADADDR(.data))
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LONG (__data_start__)
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LONG (__data_end__ - __data_start__)
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__copy_table_end__ = .;
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__zero_table_start__ = .;
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LONG (__bss_start__)
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LONG (__bss_end__ - __bss_start__)
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__zero_table_end__ = .;
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. = ALIGN(64);
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} > FLASH
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > FLASH
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.ARM.exidx :
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{
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PROVIDE_HIDDEN(__exidx_start = .);
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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PROVIDE_HIDDEN(__exidx_end = .);
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} > FLASH
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__etext = . ;
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.stack (NOLOAD) :
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{
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__StackLimit = .;
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KEEP(*(.stack .stack.*))
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. = ALIGN(1024);
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__StackTop = .;
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PROVIDE(__stack = __StackTop);
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} > SRAM
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.data : ALIGN(64)
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{
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__data_start__ = .;
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*(.ramfunc .ramfunc.*)
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. = ALIGN(8);
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*(vtable)
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. = ALIGN(8);
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*(.data .data.* .gnu.linkonce.d.*)
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. = ALIGN(8);
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__data_end__ = .;
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. = ALIGN(64);
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} > SRAM AT > FLASH
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.bss (NOLOAD) :
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{
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__bss_start__ = .;
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*(.bss .bss.* .gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(8);
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__bss_end__ = .;
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} > SRAM
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.noinit (NOLOAD) :
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{
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*(.noinit .noinit.*)
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. = ALIGN(8);
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} > SRAM
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__end__ = . ;
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PROVIDE(end = .);
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__HeapLimit = ORIGIN(SRAM) + LENGTH(SRAM);
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__FlashBase = ALIGN(LOADADDR(.data) + SIZEOF(.data), 128);
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__FlashLimit = ORIGIN(FLASH) + LENGTH(FLASH);
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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/* DWARF debug sections.
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Symbols in the DWARF debugging sections are relative to the beginning
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of the section so we begin them at 0. */
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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/* SGI/MIPS DWARF 2 extensions */
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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/* DWARF 3 */
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.debug_pubtypes 0 : { *(.debug_pubtypes) }
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.debug_ranges 0 : { *(.debug_ranges) }
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/* DWARF Extension. */
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.debug_macro 0 : { *(.debug_macro) }
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.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }
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.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
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/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
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}

‎variants/K48-S76G-I2C/openocd_scripts/s7Xg-l073rz.cfg

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# This is a ASR S7XG ASIC with STM32L073RZ, SX1276 and CXD5603GF GNSS chips.
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#
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source [find interface/stlink.cfg]
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transport select hla_swd
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# chip name
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set CHIPNAME STM32L073
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source [find target/stm32l0_dual_bank.cfg]
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reset_config srst_only connect_assert_srst

‎variants/K48-S76G-I2C/pins_arduino.h

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/*
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Copyright (c) 2014-2015 Arduino LLC. All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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// API compatibility
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#include "variant.h"
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